Abstract: A method and apparatus for implementing a power-up state initialization. A power sense circuit provides a signal for indicating when the power supply, V.sub.DD, is of a voltage level greater than the minimum voltage level suitable for safely resolving CMOS logic. The power sense signal, when asserted, enables a small, on-chip ring oscillator. An output signal generated by the ring oscillator supplies a clocking signal to the clock drivers and to the clock state machine of the CPU, thereby providing internal clocks to a central processing unit (CPU). A counter counts the number of clock pulses provided to the CPU and disables the ring oscillator and the clock state machine (thereby stopping the internal data-processor clock drivers) when the accumulated number of clock pulses equals or exceeds a predefined number. The predefined number of internal clock pulses is the minimum number of clocks to process a reset condition that resolves all on-chip, CPU state conflicts and contention.

Abstract: A system for pipelining bus requests includes a bus, at least one node coupled to the bus, and a bus coordinator coupled to the node. The node uses a single bus request signal to both request control of the bus from the bus coordinator, and to retain control of the bus. In response to an asserted bus request signal from the node, the coordinator sends an asserted bus grant signal to the node to grant the node control of the bus. This bus grant signal tracks the bus request signal so that as long as the bus request signal remains asserted, the bus grant signal also is asserted. To allow for pipelining, the bus coordinator maintains the bus grant signal in an asserted state for at least one clock cycle after the bus request is deasserted. By holding the bus grant signal in the asserted state for one extra cycle, the coordinator gives the node time to deassert and then to reassert the bus request signal before the bus grant signal changes state.

Abstract: In a disk drive storage system, an interface apparatus for controlling the transfer of sectors of data between a host processor and a buffer within the storage system in response to READ and WRITE command issued by the host processor. The apparatus comprises a Byte Count State Machine for controlling the transfer of a sector of data between the host processor and the buffer, an Update Task File State Machine for counting the sectors transferred by the Byte Count State Machine and generating the sector address of the next sector to be transferred by the Byte Count State Machine, a Read State Machine for controlling the processing of all READ commands and a Write State Machine for controlling the processing of all WRITE commands.

Abstract: A distributed data processing system includes a distributed resource manager which detects dependencies between transactions caused by conflicting lock requests. A distributed transaction manager stores a wait-for graph with nodes representing transactions and edges connecting the nodes and representing dependencies between the transactions. Each edge is labelled with the identities of the lock requests that caused the dependency. The distributed transaction manager propagates probes through the wait-for graph, to detect cyclic dependencies, indicating deadlock. A deadlock message is then sent to the resource manager identifying a particular lock request as a victim for deletion to resolve the deadlock. Resilience to failure is achieved by duplicating between agents and servers, rather than by duplicating the servers. As a result, the number of messages between agents and servers in normal operation is not increased.

Abstract: In a data processing system, a command sending module sends a command over a bus to two command executing modules at the same time, and that command is to be performed by either one, but not both, of the command executing modules.

Abstract: A method and circuit for prefetching is provided wherein selective caching of instructions occurs. An instruction execution tree comprising a plurality of instructions is traversed in a predetermined manner. Instructions depending from both paths of a conditional branch instruction are prefetched. When it is determined that a branch of prefetched instructions is not in the path of execution the instructions associated with that branch are deleted thereby pruning the branch. Instruction addresses are therefore selectively removed from a storage memory in such a manner as to provide the cache with instructions which will likely be required by the processor.

Abstract: In a pipeline processor, the identities of the highest and lowest numbered registers of a subset of general registers affected by a load multiple register (LMR) instruction are stored. The number of the lowest numbered registered of the subset is incremented as the registers are loaded. In the event that a next sequential instruction requires the contents of one of the registers in the subset, the number of the required register is compared with the incremented number and the decoding phase of the next instruction is allowed to proceed when the required register has been loaded as indicated by the incremented number. The identity of the highest numbered and the next to highest numbered registers loaded by the LMR instruction are recorded in a target register and an exclusive or-circuit is provided to determine whether the total number of registers loaded by the LMR instruction is an even number or an odd number.