Patents Examined by Jonah C Krieger
  • Patent number: 12210777
    Abstract: In some embodiments, a memory device includes a data sampler configured to sample a data signal based on a write data strobe signal, a measuring circuit configured to measure a temperature-based delay variation and a voltage-based delay variation of a transfer path of the write data strobe signal, a storage circuit configured to store a first coefficient code regulating a reference-based delay variation on the transfer path, a temperature sensor configured to sense the temperature of the transfer path, a monitoring circuit configured to generate a second coefficient code by comparing the sensed temperature, the temperature-based delay variation, the voltage-based delay variation, and the reference-based delay variation with each other, a reference voltage generator configured to generate a reference voltage, a voltage regulator configured to generate a regulation voltage, and a write data strobe signal transfer circuit configured to transfer the write data strobe signal to the data sampler.
    Type: Grant
    Filed: September 5, 2023
    Date of Patent: January 28, 2025
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kyungmin Kim, Byongmo Moon
  • Patent number: 12190970
    Abstract: A method includes determining a gap between a difference in a first health characteristic value and a second health characteristic value of blocks of memory cells and a health threshold associated with the blocks of memory cells, determining the gap is greater than or equal to a gap threshold from the health threshold, performing a pseudo media management operation on the blocks of memory cells, and determining an updated first health characteristic value of the blocks of memory cells.
    Type: Grant
    Filed: May 25, 2022
    Date of Patent: January 7, 2025
    Assignee: Micron Technology, Inc.
    Inventor: Donghua Zhou
  • Patent number: 12174985
    Abstract: A combination default write-blocking system may include a host computer. The host computer may include at least one general storage device storing program instructions for a blocking driver assembly and a host processor configured as the blocking driver assembly while executing the program instructions for the blocking driver assembly. A connection interface device physically separate from the host processor, and the connection interface device is configured to be operatively coupled to the host processor and to a protected storage device physically separate from the general storage device, receive a communication from the blocking driver assembly, and establish communication between the protected storage device and the host processor after receiving the communication from the blocking driver assembly. The blocking driver assembly is further configured to communicate with the connection interface device and conditionally allow a host computer process to alter data stored on the protected storage device.
    Type: Grant
    Filed: August 30, 2022
    Date of Patent: December 24, 2024
    Assignee: CRU Data Security Group, LLC
    Inventors: William Livengood, William M. Head, II, Dean L. Mehler
  • Patent number: 12174746
    Abstract: A data processing method, device, and storage medium that reads a parallel control code; reads, according to the parallel control code, first data that has been cached in a data cache space, processes the read first data, and outputs the processed first data to the data cache space; and simultaneously moves second data from a data storage space to the data cache space according to the parallel control code, the second data being the next data of the first data. Data processing and data moving are performed simultaneously according to the parallel control code, to reduce a duration of the data processing waiting for the data moving, thereby improving a processing speed and processing efficiency.
    Type: Grant
    Filed: October 15, 2021
    Date of Patent: December 24, 2024
    Assignee: TENCENT TECHNOLOGY (SHENZHEN) COMPANY LIMITED
    Inventor: Yu Meng
  • Patent number: 12175098
    Abstract: According to one embodiment, a storage device includes a nonvolatile memory and a controller. The controller manages first user identification information and first authentication information including a hash value calculated from the first user identification information and a first device identification information of a first client device. The controller receives an access request to the nonvolatile memory, user identification information, and authentication information transmitted from an external device, and accepts the access request in a case where the user identification information received matches the first user identification information, and the authentication information received matches the first authentication information.
    Type: Grant
    Filed: February 27, 2023
    Date of Patent: December 24, 2024
    Assignee: Kioxia Corporation
    Inventor: Hirotomo Kobayashi
  • Patent number: 12175111
    Abstract: Methods, systems, and devices for data migration techniques are described. The memory system may receive a command associated with a write operation from a host device. The memory system may determine whether to use a data migration technique for writing data to the memory device based on receiving the command. In some cases, the memory system may select a tri-level write format instead of a quad-level write format for writing the data and write the data using the tri-level write format. The memory system may convert the data from the tri-level write format to the quad-level write format based on writing the data using the tri-level write format.
    Type: Grant
    Filed: January 13, 2022
    Date of Patent: December 24, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Kulachet Tanpairoj, Jianmin Huang
  • Patent number: 12147341
    Abstract: Apparatus, method, and system provided herein are directed to prioritizing cache line writing of compressed data. The memory controller comprises a cache line compression engine that receives raw data, compresses the raw data, determines a compression rate between the raw data and the compressed data, determines whether the compression rate is greater than a predetermined rate, and outputs the compressed data as data-to-be-written if the compression rate is greater than the predetermined rate. In response to determining that the compression rate is greater than the predetermined rate, the cache line compression engine generates a compression signal indicating the data-to-be-written is the compressed data and sends the compression signal to a scheduler of a command queue in the memory controller where writing of compressed data is prioritized.
    Type: Grant
    Filed: August 6, 2020
    Date of Patent: November 19, 2024
    Assignee: Alibaba Group Holding Limited
    Inventors: Dimin Niu, Tianchan Guan, Lide Duan, Hongzhong Zheng
  • Patent number: 12147694
    Abstract: Various implementations described herein relate to systems and methods for managing metadata for conditional update, including adding conditional entry to a list in an in-memory journal for a conditional update associated with a garbage collection write, configuring a base entry in the list to point to the conditional entry, and in response to determining that the conditional update is resolved such that a physical location identified in the conditional entry is valid, freeing the conditional entry.
    Type: Grant
    Filed: August 3, 2021
    Date of Patent: November 19, 2024
    Assignee: KIOXIA CORPORATION
    Inventor: Andrew John Tomlin
  • Patent number: 12079162
    Abstract: An illustrative data storage system captures snapshots of a data structure based on snapshot creation schedules and sets retention periods for the snapshots based on snapshot retention schedules. The data storage system eradicates snapshots based on expirations of the retention periods. In certain examples, the data storage system determines a rule to use to capture a snapshot based on a state of snapshots within one or more lookback periods and/or based on a set of rules each defining a snapshot capture schedule and a snapshot retention schedule.
    Type: Grant
    Filed: June 4, 2020
    Date of Patent: September 3, 2024
    Assignee: Pure Storage, Inc.
    Inventors: Tejal Joshi Chakeres, Dirk Meister, Cheng Chang, Chu Zhang
  • Patent number: 12067241
    Abstract: A method, computer program product, and computing system for assigning flush ownership for a plurality of containers of a common frozen flushing work set to a storage processor of a pair of storage processors of a storage system. For each container of the plurality of containers of the common frozen flushing work set not assigned to a particular storage processor, the storage space of the container not assigned to the particular storage processor is reclaimed. For each container of the plurality of containers of the common frozen flushing work set assigned to a particular storage processor, data stored in the container assigned to the particular storage processor is flushed to persistent memory of the storage system.
    Type: Grant
    Filed: October 19, 2022
    Date of Patent: August 20, 2024
    Assignee: Dell Products L.P.
    Inventors: Gang Han, Vladimir Shveidel, Jibing Dong
  • Patent number: 12061795
    Abstract: This document describes aspects of communicating information about repair elements of a memory device. A memory device can include multiple repair elements that can each replace a defective or damaged memory element, such as a memory row, using a repair operation. By knowing a quantity of remaining available repair elements, a user of a memory device can make informed decisions about whether to make a replacement. In operation, a host device can send a command to the memory device requesting repair element information. Logic of the memory device can determine a quantity of repair elements that are available for a repair operation. In some cases, the logic may store this quantity in a register of the memory device. The memory device can signal the quantity of repair elements to the host device in response to the command.
    Type: Grant
    Filed: May 7, 2021
    Date of Patent: August 13, 2024
    Assignee: Micron Technologies, Inc.
    Inventors: Loren Jeffrey Wooley, Yoshinori Fujiwara, Randall James Rooney
  • Patent number: 12062406
    Abstract: A memory device includes memory blocks, a read count storage, a cell counter, and a read reclaim processor. The read count storage stores read count information including read counts of the memory blocks. When a read count of a target block among the memory blocks exceeds at least one threshold count, the cell counter performs a read operation on at least one page among pages included in the target block by using a first read voltage, and calculates a first memory cell count as a number of memory cells read as first memory cells among memory cells included in the at least one page, based on a current sensed from the at least one page in the read operation. The read reclaim processor provides a memory controller with a status code based on the first memory cell count and a number of correctable error bits.
    Type: Grant
    Filed: April 15, 2021
    Date of Patent: August 13, 2024
    Assignee: SK hynix Inc.
    Inventor: Byoung Sung You
  • Patent number: 12032843
    Abstract: A data processing system may include: a memory system comprising a memory device including a plurality of memory blocks; and a host suitable for dividing the memory device into a plurality of logical blocks, and including a plurality of segments each constituted by at least some of the plurality of logical blocks. The host may select a victim segment based on the number of the valid logical blocks corresponding to each of the memory blocks, and perform segment recycling on the victim segment, and one or more memory blocks may be invalidated by the segment recycling.
    Type: Grant
    Filed: January 25, 2021
    Date of Patent: July 9, 2024
    Assignee: SK hynix Inc.
    Inventor: Eu Joon Byun
  • Patent number: 12008242
    Abstract: A signal calibration method, a memory storage device, and a memory control circuit unit are provided. The signal calibration method includes: generating a clock signal and a data strobe signal according to an internal clock signal; respectively transmitting the clock signal and the data strobe signal to a target volatile memory module among multiple volatile memory modules through a first signal path and a second signal path; obtaining a shift value between the data strobe signal and the clock signal at the target volatile memory module; and storing an initial delay setting of the data strobe signal according to delay information of the data strobe signal in response to the shift value being greater than a threshold value.
    Type: Grant
    Filed: November 9, 2022
    Date of Patent: June 11, 2024
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Yi-Chung Chen, Ming-Chien Huang
  • Patent number: 12002508
    Abstract: The disclosure relates in some aspects to on-chip processing circuitry formed within the die of a non-volatile (NVM) array to perform data searches. In some aspects, the die includes components configured to sense wordlines of stored data in the NVM array by applying voltages on the wordlines serially, and then search for an input data pattern within the serially-sensed wordlines. In some examples, the components of the die include latches and circuits configured to perform bitwise latch logic search operations. In other examples, the search components are configured with under-the-array or next-to-the-array dedicated search circuitry that uses registers and/or random access memory (RAM). Other aspects relate to a separate controller device for controlling the on-chip NVM search operations. For example, the controller may determine whether to search for data using search components of the NVM die or processors of the controller based, e.g., on a degree of fragmentation of data.
    Type: Grant
    Filed: October 14, 2021
    Date of Patent: June 4, 2024
    Assignee: Western Digital Technologies, Inc.
    Inventors: Eran Sharon, Alon Marcu, Shay Benisty, Judah Gamliel Hahn, Idan Alrod, Alexander Bazarsky, Ariel Navon, Ran Zamir
  • Patent number: 11977747
    Abstract: The present invention discloses a memory access apparatus having address scrambling mechanism that includes an address scrambling circuit and a memory controller. The address scrambling circuit performs the steps outlined below. An original access address is received to be interpreted into original unit indexes and a minimal original unit according to regional unit levels of a memory. Scrambled unit indexes and a minimal scrambled unit are generated correspondingly according to a random address generation algorithm, to further generate a scrambled access address accordingly, in which when a plurality of different original access addresses have at least one the same original unit indexes from the highest block unit level, the scrambled unit indexes generated therefrom are the same. The memory controller accesses the memory according to the scrambled access address.
    Type: Grant
    Filed: October 26, 2021
    Date of Patent: May 7, 2024
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Shiue-Ru Wu, Ching-Tung Wu
  • Patent number: 11954360
    Abstract: Systems, apparatuses and methods may provide for technology that programs a plurality of seed values into a plurality of linear feedback shift registers (LFSRs), wherein the plurality of LFSRs correspond to a data word (DWORD) and at least two of the plurality of seed values differ from one another. The technology may also train a link coupled to the plurality of LFSRs, wherein the plurality of seed values cause a parity bit associated with the DWORD to toggle while the link is being trained. In one example, the technology also automatically selects the plurality of seed values based on one or more of an expected traffic pattern on the link (e.g., after training) or a deskew constraint associated with the link.
    Type: Grant
    Filed: September 1, 2020
    Date of Patent: April 9, 2024
    Assignee: Intel Corporation
    Inventors: Narasimha Lanka, Kuljit Bains, Lohit Yerva
  • Patent number: 11909423
    Abstract: According to one embodiment, a compression circuit generates substrings from input data for (3+M) cycles, the input data being N bytes per cycle, a byte length of each substring being greater than or equal to (NĂ—(1+M)+1); obtains a set of matches, each of the matches including at least one past input data which input past and corresponds to at least a part of each of the substrings; selects a subset of matches from the set of matches including the input data of one cycle; and outputs the subset of matches. M is zero or a natural number. N is a positive integer which is two or more.
    Type: Grant
    Filed: March 14, 2022
    Date of Patent: February 20, 2024
    Assignee: Kioxia Corporation
    Inventors: Sho Kodama, Keiri Nakanishi, Daisuke Yashima
  • Patent number: 11899959
    Abstract: A method of testing a memory device, a memory built-in self-test (MBIST) circuit, and a memory device for improving reliability and reducing a test time. The memory device includes a plurality of memory banks and the MBIST circuit. The MBIST circuit is configured to generate double data rate (DDR) test patterns and parallel bit test (PBT) test patterns to test the memory banks. When a defective cell is detected as a result of the PBT test or the DDR test, the MBIST circuit is configured to perform a repair operation for replacing the defective cell with a redundancy cell and perform a re-test to verify the repair operation. The MBIST circuit may be configured to perform the DDR test on one or more memory cells including the defective cell during the re-test.
    Type: Grant
    Filed: June 3, 2021
    Date of Patent: February 13, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jaewon Park, Sangkil Park, Jaehoon Lee
  • Patent number: 11880611
    Abstract: A data process device includes a data input unit and a processor. The processor includes a division unit, a first storage unit and a second storage unit which have a plurality of storage areas, a write unit, a calculation unit, and a control unit. The division unit divides a data series input by the data input unit to generate a plurality of divided data. The write unit writes the divided data to the first storage unit according to writing order to the storage areas in the first storage unit. The calculation unit performs calculation processing on the divided data written to the first storage unit, and writes calculated data obtained by the calculation processing to the second storage unit according to writing order to the storage areas in the second storage unit. The control unit controls processing of the write unit and processing of the calculation unit, which are divided into different processing lines, to be executed in parallel by pipeline processing.
    Type: Grant
    Filed: June 18, 2019
    Date of Patent: January 23, 2024
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventors: Takahiro Suzuki, Sang-Yuep Kim, Junichi Kani