Patents Examined by Jonah C Krieger
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Patent number: 11429416Abstract: Methods, systems, and computer program products are included for de-duplicating one or more memory pages. A method includes receiving, by a hypervisor, a list of read-only memory page hints from a guest running on a virtual machine. The list of read-only memory page hints specifies a first memory page marked as writeable. The method also includes determining whether the first memory page matches a second memory page. In response to a determination that the first memory page matches the second memory page, the hypervisor may deduplicate the first and second memory pages.Type: GrantFiled: April 15, 2019Date of Patent: August 30, 2022Assignee: RED HAT ISRAEL, LTD.Inventors: Michael Tsirkin, Uri Lublin
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Patent number: 11422739Abstract: A memory controller controls a memory device including a memory cell array, and includes: a message information generator configured to receive a first request message from a host, and generate and output response characteristic information indicating a type of the first request message that defines a response time within which a message response to the first request message is provided to the host and a response output controller configured to determine, based on the response characteristic information, a time at which the message response corresponding to the first request message is output to the host.Type: GrantFiled: July 12, 2019Date of Patent: August 23, 2022Assignee: SK hynix Inc.Inventor: Hung Yung Cho
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Patent number: 11416162Abstract: The present application relates to a garbage collection method and a storage device for reducing write amplification. A method for selecting a data block to be collected in garbage collection, including: obtaining, according to a first selection policy, a first data block to be collected; determining, according to a first rejection policy, whether to refuse to collect the first data block to be collected; and if according to the first rejection policy, rejection to collect of the first data block to be collected is determined, not performing garbage collection on the first data block to be collected.Type: GrantFiled: June 27, 2018Date of Patent: August 16, 2022Assignee: BEIJING MEMBLAZE TECHNOLOGY CO., LTDInventors: Jinyi Wang, Xiangfeng Lu
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Patent number: 11347397Abstract: Embodiments of the present disclosure relate to traffic class management of NVMe (non-volatile memory express) traffic. One or more input/output (I/O) operations are received at a device interface coupled to one or more storage devices of a storage array. A service level (SL) corresponding to each of the one or more I/O operations is determined. Each of the one or more I/O operations is transmitted to the one or storage devices over a virtual channel of a set of virtual channels based on the determined SL corresponding to each of the one or more I/O operations.Type: GrantFiled: October 1, 2019Date of Patent: May 31, 2022Assignee: EMC IP Holding Company LLCInventors: Owen Martin, Arieh Don
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Patent number: 11334287Abstract: A computer system having a host in communication with a data storage device is coupled to the host via a peripheral bus and a host interface. The data storage device has a controller, non-volatile storage media; and firmware containing instructions configures the operations of the controller. The host transmits a sequence of commands to the storage device to read data items from, or write data items to, the non-volatile storage media. The storage device examines a subset of the commands to determine whether or not data items identified in the subset are addressed sequentially and optimizes processing of at least a portion of the sequence of commands based on a result of a determination of whether or not data items identified in the subset are addressed sequentially.Type: GrantFiled: February 9, 2018Date of Patent: May 17, 2022Assignee: Micron Technology, Inc.Inventor: Alex Frolikov
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Patent number: 11327656Abstract: A method for accessing a dynamic memory module, the method may include (i) receiving, by a memory controller, a set of access requests for accessing the dynamic memory module; (ii) converting the access requests to a set of commands, wherein the set of commands comprise (a) a first sub-set of commands that are related to a first group of memory banks, and (b) a second sub-set of commands that are related to a second group of memory banks; (iii) scheduling, by a scheduler of the memory controller, an execution of the first sub-set; (iv) scheduling an execution of the second sub-set to be interleaved with the execution of the first sub-set; and (v) executing the set of commands according to the schedule.Type: GrantFiled: August 2, 2019Date of Patent: May 10, 2022Assignee: Mobileye Vision Technologies Ltd.Inventors: Boris Shulman, Yosef Kreinin, Leonid Smolyansky
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Patent number: 11314449Abstract: In some examples, a tracker receives a write request that is acknowledged upon receipt by a destination media controller without waiting for achievement of persistence of write data associated with the write request. The tracker adds an identifier of the destination media controller to a tracking structure in response to the identifier not already being present in the tracking structure. The tracker sends a request to persist write operations to media controllers identified by the tracking structure.Type: GrantFiled: May 18, 2020Date of Patent: April 26, 2022Assignee: Hewlett Packard Enterprise Development LPInventor: Derek Alan Sherlock
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Patent number: 11314442Abstract: A method for determining to rebuild a namespace. The method includes one or more computer processors identifying a set of storage devices associated with the namespace of the user. The method further includes determining a state of health of a namespace based on information related to the set of storage devices associated with the namespace and further includes identifying a set of criteria related to the state of health of the namespace. The method further includes responding to determining that one or more criteria related to the state of health of namespace attains respective trigger values by replacing a first set of storage devices that store data corresponding to the namespace and are included among one or more storage systems. The method further includes dictating to replace the first set of storage devices that store data corresponding to the namespace and are included among the one or more storage systems.Type: GrantFiled: December 4, 2019Date of Patent: April 26, 2022Assignee: International Business Machines CorporationInventors: Asimuddin Kazi, Ethan Wozniak
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Patent number: 11281608Abstract: Systems and techniques for a translation device that is configured to enable communication between a host device and a memory technology using different communication protocols (e.g., a communication protocol that is not preconfigured in the host device) is described herein. The translation device may be configured to receive signals from the host device using a first communication protocol and transmit signals to the memory device using a second communication protocol, or vice-versa. When converting signals between different communication protocols, the translation device may be configured to convert commands, map memory addresses to new addresses, map between channels having different characteristics, encode data using different modulation schemes, or a combination thereof.Type: GrantFiled: August 8, 2018Date of Patent: March 22, 2022Assignee: Micron Technology, Inc.Inventors: Brent Keeth, Richard C. Murphy, Elliott C. Cooper-Balis
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Patent number: 11262940Abstract: An operating method for a controller includes: receiving a target command; detecting a first command from a first command queue, the first command having a same logical address as the target command; queuing the target command in the first command queue when the first command is not detected from the first command queue; detecting, when the first command queue is full of commands, a second command from a second command queue, the second command having the same logical address as the target command; and queuing the target command in the second command queue, when the second command is not detected from the second command queue.Type: GrantFiled: April 12, 2019Date of Patent: March 1, 2022Assignee: SK hynix Inc.Inventors: Soong-Sun Shin, Jin-Soo Kim, Han Choi
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Patent number: 11262950Abstract: A memory system containing: a nonvolatile memory device including a plurality of memory dies that each perform a plurality of command operations, and a controller configured to: store, in a preset internal space, profile information for changes in power consumption for each of a operation sections included in each of the command operations, check, from the profile information, the changes in power consumption for each operation section of a first and second command when sequentially propagating the first and second command to the memory dies, calculate, based on the checked changes in power consumption for each operation section, a maximum length of an overlap operation section between the first and second command in which peak power is maintained at or below a first reference power, and adjust, a difference between time points for performing the first and second command based on the calculated maximum length of the overlap operation section.Type: GrantFiled: July 27, 2020Date of Patent: March 1, 2022Assignee: SK hynix Inc.Inventor: Dong Yeob Chun
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Patent number: 11200945Abstract: A plurality of memory cells are arranged along a plurality of bit lines and a plurality of word lines. A sense amplifier is connected to each of the bit lines. Arranged along each bit line are at least four memory cells including first to fourth memory cells that are either connected to or disconnected from one of the bit lines by means of first to fourth switching elements according to an active or inactive state of first to fourth word lines. The first memory cell stores a first bit value, the second memory cell stores a second bit value, and the third and fourth memory cells each store a third bit value. A memory cell array control circuit activates and then deactivates the third and fourth word lines, subsequently activates the first and second word lines, and then activates the sense amplifier.Type: GrantFiled: January 31, 2017Date of Patent: December 14, 2021Assignee: ZENTEL JAPAN CORPORATIONInventors: Takashi Kubo, Masaru Haraguchi, Takeshi Hamamoto, Kenichi Yasuda, Yasuhiko Tsukikawa, Hironori Iga
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Patent number: 11158369Abstract: The disclosure relates in some aspects to on-chip processing circuitry formed within the die of a non-volatile (NVM) array to perform data searches. In some aspects, the die includes components configured to sense wordlines of stored data in the NVM array by applying voltages on the wordlines serially, and then search for an input data pattern within the serially-sensed wordlines. In some examples, the components of the die include latches and circuits configured to perform bitwise latch logic search operations. In other examples, the search components are configured with under-the-array or next-to-the-array dedicated search circuitry that uses registers and/or random access memory (RAM). Other aspects relate to a separate controller device for controlling the on-chip NVM search operations. For example, the controller may determine whether to search for data using search components of the NVM die or processors of the controller based, e.g., on a degree of fragmentation of data.Type: GrantFiled: December 26, 2018Date of Patent: October 26, 2021Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Eran Sharon, Alon Marcu, Shay Benisty, Judah Gamliel Hahn, Idan Alrod, Alexander Bazarsky, Ariel Navon, Ran Zamir
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Patent number: 11157189Abstract: An information handling system may include at least one processor and a memory coupled to the at least one processor. The information handling system may be configured to receive data comprising a plurality of data chunks; perform deduplication on the plurality of data chunks to produce a plurality of unique data chunks; determine a compression ratio for respective pairs of the unique data chunks; determine a desired compression order for the plurality of unique data chunks based on the compression ratios; combine the plurality of unique data chunks in the desired compression order; and perform data compression on the combined plurality of unique data chunks.Type: GrantFiled: July 10, 2019Date of Patent: October 26, 2021Assignee: Dell Products L.P.Inventor: Venkata L. R. Ippatapu
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Patent number: 11133067Abstract: Disclosed are systems and methods for providing multi-phased programming with balanced Gray coding. A method includes programming, in a first phase, a first portion of data into memory cells of a flash memory in a first-level cell mode. The method also includes retaining, in a cache, at least a subset of the data. The method also includes regenerating the data from at least the cache, wherein the regenerated data includes a second portion of the data. The method also includes programming, in a second phase, the regenerated data in a second-level cell mode based on a mapping from the first-level cell mode to the second-level cell mode. The mapping maps each state distribution in the first-level cell mode to at least two non-adjacent state distributions in the second-level cell mode, and a width of each state distribution in the first-level cell mode may be narrowed.Type: GrantFiled: March 8, 2019Date of Patent: September 28, 2021Assignee: Western Digital Technologies, Inc.Inventors: Sergey Anatolievich Gorobets, Xinmiao Zhang, James Fitzpatrick
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Patent number: 11119915Abstract: A method to map a plurality of feature maps of a neural network onto a memory hierarchy includes mapping a first feature map of the plurality of feature maps to a memory in a memory hierarchy having available memory space and providing quickest access to the first feature map. The method also includes, when the first feature map expires, removing the first feature map from the memory used to store the first feature map.Type: GrantFiled: February 8, 2018Date of Patent: September 14, 2021Assignee: Samsung Electronics Co., Ltd.Inventors: Chenchi Luo, Hyejung Kim, Seok-Jun Lee, David Liu, Michael Polley
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Patent number: 11096578Abstract: A device includes an overlay mechanism, system with devices each including an overlay mechanism with an individually programmable delay or method for overlaying data. A method for overlaying data includes redirecting an access which is directed to a first memory location to a second memory location. The method for overlaying data selectively delays access to the second memory location in case of a redirection by a time.Type: GrantFiled: May 15, 2020Date of Patent: August 24, 2021Assignee: Infineon Technologies AGInventor: Neil Stuart Hastie
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Patent number: 11086724Abstract: Embodiments for a method of backing up virtual hard disks by: parsing a list of base parent and differencing disks to identify disk parameters and child disks of immediate parent disks; creating a differencing disk chain in reverse time order of modification of the base parent disk starting from the base parent disk to a latest child differencing disk; identifying changed sectors in each child disk starting from the latest child differencing disk; creating a list detailing a respective differencing disk, sector offsets and logical data sector index for each changed sector; iteratively adding updated sectors to the list for latest changed sectors that were not previously added to the list by a later child disk by reading the changed sectors from their respective child disk; and merging, in a single step, the changed sectors read from their respective child disks into the base parent disk.Type: GrantFiled: October 18, 2017Date of Patent: August 10, 2021Assignee: EMC IP Holding Company LLCInventors: Suman C Tokuri, Pradeep Anappa, Sunil Yadav, Soumen Acharya, Sudha V Hebsur, Aaditya R Bansal
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Patent number: 11010302Abstract: A mechanism is described for facilitating general purpose input/output data capture and neutral cache system for autonomous machines. A method of embodiments, as described herein, includes capturing, by an image capturing device, one or more images of one or more objects, where the one or more images represent input data associated with a neural network. The method may further include determining accuracy of first output results generated by a default neural caching system by comparing the first output results with second output results predicted by a custom neural caching system. The method may further include outputting, based on the accuracy, a final output results including at least one of the first output results or the second output results.Type: GrantFiled: October 5, 2016Date of Patent: May 18, 2021Assignee: INTEL CORPORATIONInventors: Liwei Ma, Jiqiang Song
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Patent number: 10983909Abstract: Certain aspects provide systems and methods for performing an operation on a B?-tree. A method comprises writing a message associated with the operation to a first slot in a first buffer of a first non-leaf node of the B?-tree in an append-only manner, wherein a first filter associated with the first slot is used for query operations associated with the first slot. The method further comprises determining that the first buffer is full and, upon determining to flush the message to a non-leaf child node, flushing the message in an append-only manner to a second slot in a second buffer of the non-leaf child node, wherein a second filter associated with the second slot is used for query operations associated with the second slot. The method further comprises, upon determining to flush the message to a leaf node, flushing the message to the leaf node in a sorted manner.Type: GrantFiled: January 18, 2019Date of Patent: April 20, 2021Assignee: VMware, Inc.Inventors: Abhishek Gupta, Robert T. Johnson, Richard P. Spillane, Sandeep Rangaswamy, Jorge Guerra Delgado, Kapil Chowksey, Srinath Premachandran