Patents Examined by Joni Y. Chang
  • Patent number: 5668031
    Abstract: A method of fabricating a high density flat mask read only memory. At first a plurality of trenches are formed in a surface of a silicon substrate at predetermined desired source-drain electrodes areas. A dielectric layer is formed on at least the surface of the trenches. A first polysilicon layer is formed over the dielectric layer and then portions of the first polysilicon layer are removed to leave a portion thereof on the bottom of each trench. Using the first polysilicon layer as an etch stop layer, the dielectric layer is etched. A second polysilicon layer then is formed on the surface of the silicon substrate, the first polysilicon layer and the dielectric layer, and then the the second polysilicon layer is etched back to the substrate surface to form the source-drain electrode areas, that is, the bit lines. On the surface of the bit lines and the silicon substrate, a gate oxide layer and a third polysilicon layer are formed sequentially.
    Type: Grant
    Filed: June 4, 1996
    Date of Patent: September 16, 1997
    Assignee: United Microelectronics Corp.
    Inventors: Chen-Chiu Hsue, Cheng-Hui Chung, Yi-Chung Sheng
  • Patent number: 5665166
    Abstract: Disclosed is a plasma processing apparatus, comprising a first electrode on which an object to be processed is to be disposed, a second electrode arranged to face the first electrode, a high frequency power supply for supplying a high frequency power between the first and second electrodes, a processing gas supplying mechanism for forming a plasma into a region between the first and second electrodes, and a bias potential detecting mechanism for detecting the bias potential of the first electrode. The bias detecting mechanism has a detecting terminal positioned in the vicinity of the object to be processed.
    Type: Grant
    Filed: October 23, 1996
    Date of Patent: September 9, 1997
    Assignee: Tokyo Electron Limited
    Inventors: Youichi Deguchi, Satoru Kawakami, Yoichi Ueda, Mitsuaki Komino
  • Patent number: 5662741
    Abstract: The present invention is directed to a process for ionizing material vapors generated thermally at reduced pressure, characterized in that the material vapors are exposed to electrons from the cathode spots 6 of a self-consuming cold cathode 3, 4, the thermal vaporization device 7 being connected as an anode, so that a vacuum arc discharge forms between cathode 3, 4 and anode 7. Another objective of the invention is a device for operating said process, wherein in a vacuum chamber 1, there is arranged a coolable cathode holder 3 having the cathode material 4 applied thereon for generating cathode spots on the self-consuming cold cathode, a thermal material vaporization system 7, 8, 9 connected as an anode, a wall 10 surrounding the cathode and connected as an auxiliary anode, which wall has an opening opposite the cathode.
    Type: Grant
    Filed: September 22, 1994
    Date of Patent: September 2, 1997
    Assignee: Plasco Dr. Ehrich Plasma-Coating GmbH
    Inventor: Horst Ehrich
  • Patent number: 5660639
    Abstract: An improved plasma treatment apparatus and method are provided, wherein the flow of ionizable gas across an article surface to be treated is optimized through the use of one or more flow lines having a plurality of distribution orifices therealong. The flow lines closely conform to at least one contour of the article surface.
    Type: Grant
    Filed: October 17, 1995
    Date of Patent: August 26, 1997
    Assignee: Ford Motor Company
    Inventors: Lawrence F. Wilski, Michael D. Tisack
  • Patent number: 5661063
    Abstract: A semiconductor memory device provided with capacitors formed above and below a cell transistor includes first and second transistors formed in a first level, a first storage electrode connected to the first transistor and formed below the first level, and a second storage electrode connected to the second transistor and formed above the first level. The first and second storage electrodes are connected to each source via a spacer formed on the sidewalls of each source, and undercuts are formed between the storage electrode and the transistor, to thereby obtain double or more cell capacitance, stable cell transistor characteristic and reduced short-channel effects.
    Type: Grant
    Filed: October 19, 1995
    Date of Patent: August 26, 1997
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Joo-young Lee
  • Patent number: 5658389
    Abstract: According to a thin film forming method, at least one type of gas is activated to produce a plurality of species having positive or negative charges. The plurality of species pass through an electric field or magnetic field to extract specific species. The specific species are supplied to a substrate surface. Thereafter, the specific species are chemically reacted with each other to form a thin film. This extraction is performed using a difference in track corresponding to a ratio of mass to charge of the species passing through the electric field.
    Type: Grant
    Filed: October 15, 1993
    Date of Patent: August 19, 1997
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tetsuo Matsuda, Haruo Okano, Tokuhisa Ohiwa
  • Patent number: 5656123
    Abstract: The present invention is directed to a dual frequency capacitively-coupled plasma apparatus for materials processing. According to a first aspect of the present invention, a dual frequency triode reactor includes a VHF (30-300 MHz) RF power supply capacitively coupled to an upper reactor electrode and an HF (0.1-30 MHz) RF power supply capacitively coupled to a lower reactor electrode to which the wafer is attached. The VHF power supply is used to generate and control formation of a low sheath potential, high density plasma for minimum device damage and rapid etching/deposition while the HF power supply is used to provide a DC bias to the wafer substrate. According to a second aspect of the present invention, a tailored, powered upper electrode, at least a portion of which is generally conical in shape, is employed to provide a uniform etch across the diameter of the wafer.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: August 12, 1997
    Assignee: Varian Associates, Inc.
    Inventors: Siamak Salimian, Carol M. Heller, Lumin Li
  • Patent number: 5656529
    Abstract: In a method for manufacturing a capacitor, a lower electrode is formed by an amorphous refractory metal silicide layer and its underlying conductive layer, a heating operation is performed upon the amorphous refractory metal silicide layer, so that the amorphous refractory metal silicide layer is converted into a polycrystalline refractory metal layer having an uneven surface.
    Type: Grant
    Filed: May 10, 1996
    Date of Patent: August 12, 1997
    Assignee: NEC Corporation
    Inventor: Tadashi Fukase
  • Patent number: 5653810
    Abstract: An apparatus for forming metal film for forming metal films on substrates comprises a reaction chamber, a plurality of first and second electrodes alternately arranged in the reaction chamber, an energy supply means that supplies to the first and second electrodes an electrical energy for generating plasma, a heating means for heating a plurality of substrates disposed between the first and second electrodes, and a gas feed means that feeds into the reaction chamber a starting material gas for forming metal films; the plasma is generated across the first and second electrodes to form metal films on the plurality of substrates.The apparatus can form metal films at a high throughput at one time process, and at a low cost.
    Type: Grant
    Filed: March 17, 1995
    Date of Patent: August 5, 1997
    Assignee: Canon Kabushiki Kaisha
    Inventors: Yuzo Kataoka, Yukihiro Hayakawa
  • Patent number: 5653811
    Abstract: A plasma system for processing large area substrates. In one embodiment the system includes a plurality of radiofrequency (rf) plasma sources removably attached to the rf transparent windows of a processing chamber. The number and distribution of sources is varied to provide the size and uniformity of the plasma field required to treat the substrate. A plurality of plasma probes, such as Langmuir probes, Faraday cups and optical sensor are positioned within the chamber and in electrical communication with the plasma sources adjust the rf field produced by the individual sources to maintain the desired degree of field uniformity.
    Type: Grant
    Filed: July 19, 1995
    Date of Patent: August 5, 1997
    Inventor: Chung Chan
  • Patent number: 5653812
    Abstract: The invention is a method and apparatus for the RF plasma deposition of diamond-like carbon (DLC) and related hard coatings onto the surface of drills; especially microdrills such as printed circuit board drills and printed wire board drills, using a mounting means connected to a source of capacitively coupled RF power. A key feature of the apparatus is that the drills to be coated are the only negatively biased surfaces in the capacitively-coupled system.According to the method, the surface of the drills to be coated are first chemically de-greased to remove contaminants, and inserted into the electronically masked coating fixture of the present invention. The electronically masked fixture includes the powered electrode, the portion of the drills to be coated, an electrically insulated spacer, and an electrically grounded shield plate. Next, the loaded fixture is placed into a plasma deposition vacuum chamber, and the air in said chamber is evacuated.
    Type: Grant
    Filed: September 26, 1995
    Date of Patent: August 5, 1997
    Assignee: Monsanto Company
    Inventors: Rudolph Hugo Petrmichl, Ray Hays Venable, Rickey Leonard Salter, Victor M. Zeeman, Jr.
  • Patent number: 5651826
    Abstract: A plasma processing apparatus is provided with a plasma generating mechanism including an electric discharge chamber and an annular antenna, a plasma diffusion chamber for diffusing plasma generated by the plasma generating mechanism for processing a substrate, a first temperature adjusting mechanism for adjusting the temperature of the plasma diffusion chamber, a magnetic field generating mechanism arranged around the plasma diffusion chamber to generate a magnetic field in the plasma diffusion chamber, an evacuating mechanism, a gas introducing mechanism, and a substrate holding mechanism. The magnetic field generating mechanism includes permanent magnets and a yoke, and a heat insulating portion is formed between the permanent magnets and the plasma diffusion chamber. A second temperature adjusting mechanism for adjusting the temperature of the permanent magnets is used.
    Type: Grant
    Filed: May 23, 1996
    Date of Patent: July 29, 1997
    Assignee: Anelva Corporation
    Inventor: Ken-ichi Takagi
  • Patent number: 5651825
    Abstract: A plasma material gas is introduced into a plasma producing chamber, and, if necessary, a processing gas is introduced into a processing chamber communicated with the plasma producing chamber. In the plasma producing chamber, a microwave is radiated to a sintered body of metal oxide forming a plasma source, so that plasma is generated from the plasma material gas. Ions generated thereby are accelerated and introduced into the processing chamber. Predetermined processing is performed on a work directly by the ions, or is performed in a plasma generated by the ions from the processing gas.
    Type: Grant
    Filed: March 1, 1995
    Date of Patent: July 29, 1997
    Assignee: Nissin Electric Co., Ltd.
    Inventors: Takahiro Nakahigashi, Hajime Kuwahara
  • Patent number: 5652029
    Abstract: In a plasma processing apparatus including a cylindrical electrode and plural electrodes which are disposed to face the cylindrical electrode in a circumferential direction of the cylindrical electrode, the plural electrodes are designed to have the prescribed curvature corresponding to that of the surface of the cylindrical electrode. The interval between the cylindrical electrode and the plural electrodes may be fixed or stepwise varied in the circumferential direction. The area of each of the plural electrodes may be different from that of the other electrodes.
    Type: Grant
    Filed: March 23, 1995
    Date of Patent: July 29, 1997
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Kenji Itoh
  • Patent number: 5650039
    Abstract: A chemical mechanical polishing apparatus polishes substrates on a rotating polishing pad in the presence of a chemically active and/or physically abrasive slurry. At least one groove is provided in the surface of the polishing pad to allow slurry to reach the surface of the substrate, which is engaged with the polishing pad. The groove extends at least partially in a radial direction. Additionally, a pad conditioning apparatus may be placed onto the rotating polishing pad as substrates are being polished to continuously condition the polishing pad.
    Type: Grant
    Filed: March 2, 1994
    Date of Patent: July 22, 1997
    Assignee: Applied Materials, Inc.
    Inventor: Homayoun Talieh
  • Patent number: 5650013
    Abstract: A chemical vapor reaction processing apparatus including a reaction chamber; a power source; a source of a reactive film forming gas; a device for inputting the reactive film forming gas into the chamber; a pair of electrodes connected to the power source, at least a portion of the pair of electrodes being provided in the reaction chamber; a power source for supplying a first electric power into the reaction chamber through the pair of electrodes to generate a plasma of the reactive film forming gas in the chamber for providing a plasma CVD deposition of the reactive film forming gas on a surface; a source of a reactive cleaning gas; a device for inputting the reactive cleaning gas into the chamber where the power source supplies a second electric power into the reaction chamber through the pair of electrodes to generate a plasma of the reactive cleaning gas in the chamber so that an inner wall of the chamber is cleaned by the plasma.
    Type: Grant
    Filed: November 30, 1994
    Date of Patent: July 22, 1997
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 5647964
    Abstract: An improved diamond film synthesizing apparatus and a method thereof using a direct current glow discharge plasma enhanced chemical vapor deposition advantageously providing a plurality of cathodes for forming a relatively large plasma size, which includes a reactor having an upper wall and a bottom wall; a plurality of spaced apart cathode holders half inserted into the upper wall of the reactor, arranged in a triangle when looking dowawardly over the head of the reactor; a plurality of cathode connecting rods, each of which is threadly connected to the cathode holders inside the reactor, respectively; a plurality of cathodes, each of which is threadly connected to the cathode connecting rods, respectively; an anode half inserted into the bottom wall of the reactor and having a substrate attached on the top thereof, whereby all the cathodes and the anodes are spaced apart inside the reactor by a predetermined distance; and a gas supplier connected to one side wall of the reactor having a circular gas supplyi
    Type: Grant
    Filed: June 2, 1995
    Date of Patent: July 15, 1997
    Assignee: Korea Institute of Science and Technology
    Inventors: Jae-Kap Lee, Young-Joon Baik, Kwang Yong Eun
  • Patent number: 5647912
    Abstract: A permeable container having a plurality of holes whose diameters are equal to or less than two times the sheath length is provided in a vacuum container. provided at the bottom of this permeable container is an electrode on which an object to be processed is to be placed. A high-frequency power supply is connected to this electrode, and the permeable container is grounded. The permeable container and the electrode are insulated from each other by an insulator. When a process gas supplied into the vacuum container is guided into the permeable container through its holes and a high-frequency voltage is applied to the electrode, plasma is produced in the permeable container. Because the diameters of the holes are equal to or less than two times the sheath length, plasma is trapped inside the permeable container, thus improving the stability and density of plasma.
    Type: Grant
    Filed: April 1, 1996
    Date of Patent: July 15, 1997
    Assignee: NEC Corporation
    Inventors: Takahiro Kaminishizono, Takeshi Akimoto
  • Patent number: 5647913
    Abstract: A plasma reactor includes, a) an electrically insulative shell forming a reactor cavity, the reactor cavity having internal walls; b) inductive coils positioned externally of the cavity; and c) a capacitive coupling plate positioned externally of the cavity intermediate the cavity and inductive coils, a power source being operably connected with the capacitive coupling plate. A method of cleaning away material adhering to internal walls of a plasma reactor includes, a) injecting a cleaning gas into the reactor, the cleaning gas comprising a species which when ionized is reactive with material adhering to the internal plasma reactor walls; and b) generating a capacitive coupling effect between a pair of conductors, at least one of which is positioned externally of the plasma reactor, effective to both ionize the cleaning gas into the reactive ionized species and draw such ionized species in the direction of the external conductor to impact and clean away material adhering to the reactor internal walls.
    Type: Grant
    Filed: May 25, 1995
    Date of Patent: July 15, 1997
    Assignee: Micron Technology, Inc.
    Inventor: Guy Blalock
  • Patent number: 5648291
    Abstract: The present invention provides a method of manufacturing a bit line for a three polysilicon layer DRAM. The method begins by providing a drain region between two spaced transfer gates on a substrate, a first silicon oxide insulation layer over the drain, a capacitor having a polysilicon top plate, the polysilicon top plate extending over the drain, and an inter metal dielectric layer over the resultant structure. First, a bit line contact opening is formed in the inter metal dielectric layer stopping at the top plate over the drain. Next, anisotropic polysilicon etch is used to remove the top plate over the drain. Third, dielectric spacers are formed on the sidewalls of the bit line opening. Fourth, the bitline opening lined by the spacers is filled with a metal to contact the bit line. The spacers insulate the plate electrode from the bit line. Also, the spacers allow a smaller bit line to be used thereby making the memory cell smaller.
    Type: Grant
    Filed: June 3, 1996
    Date of Patent: July 15, 1997
    Assignee: Vanguard International Semiconductor Corporation
    Inventor: Jan Mye Sung