Abstract: A communications receiver system is presented for detecting burst errors and providing erasure information to the block decoder, thereby effectively doubling the conventional correction capability of the block decoder with only a minimal increase in complexity. In one embodiment, the receiver includes a demodulator modified to detect error bursts in the received symbol sequence. Once detected, the locations of symbols in error are marked in the form of erasure flags. An error correction decoder is then able to correct up to twice as many errors with the additional information provided by the erasure flags.

Abstract: A multi-level security apparatus and method for a network employs a secure network interface unit (SNIU) coupled between each host or user computer unit and a network, and a security management (SM) architecture, including a security manager (SM) coupled to the network, for controlling the operation and configuration of the SNIUs coupled to the network. Each SNIU is operative at a session level of interconnection which occurs when a user on the network is identified and a communication session is to commence. When an SNIU is implemented at each computer unit on the network, a global security perimeter is provided. In a preferred embodiment, the SNIU is configured to perform a defined session level protocol (SLP), including the core functions of user interface, session manager, dialog manager, association manager and data sealer, and network interface.

Abstract: The invention relates to the alteration of a segment and an offset used to form an effective address of the default interrupt handler routine. The method comprising a number of steps. First, a trap address of a default interrupt handler routine is provided. This trap address includes a segment and an offset normally used to calculate the effective address via conventional circuitry. However, an unique segment is produced by performing an arithmetic operation on the segment. Thereafter, another arithmetic operation is performed to produce a unique segment. These unique segment and offset values may still be used by the conventional circuitry to still produce the same effective addresses so that only one default interrupt handler routine is required. While this alteration produces a unique segment and offset which can be assigned to an interrupt, the segment and offset are modified appropriately to still use a common default interrupt handler.

Abstract: A method and apparatus are disclosed for powering-up a microprocessor in a system under debugger control. The microprocessor comprises I/O connection pins, internal logic, and a reset condition responsive to a reset signal. Additionally, the microprocessor has a boundary scan architecture, such as an IEEE 1149.1 (JTAG) compliant interface, which includes a boundary scan register (BSR) and at least one design-specific test data register. The BSR has normal and test modes. In the normal mode, the BSR operatively connects the internal logic to the I/O connection pins. In the test mode, the BSR operatively isolates the internal logic from the I/O connection pins. The method comprising first detecting when power is applied to the microprocessor. Once power is detected and while the microprocessor remains in the reset condition, the BSR is put into tile test mode to isolate the internal logic from the I/O connection pins.

Abstract: In a security level control apparatus for controlling a security level of a communication established between communication parties, this security level control apparatus is arranged by employing a security level recognizing unit and a security level setting unit. The security level recognizing unit recognizes a security level notified from a communication party. The security level setting unit sets the security level recognized by the security level recognizing unit as a security level for the security level control apparatus. In accordance with this security level control apparatus, the security level of the communication party recognized by the security level recognizing unit is first set as the security level for the security level control apparatus. As a result, the communication can be established between the communication parties without presetting the security level.

Abstract: The present invention aims to execute customization for each user in case portable media for computer published in large quantity are used in combination with a network. The information to control corresponding relation between portable media and users is substituted by media-identifying information 101 different for each medium among media-related information 100 set to the portable media in advance, and this is used for the control of the users. Thus, there is no need to register the users, and customization for each user can be improved.

Abstract: A breakpoint unit contains a memory circuit which monitors digital signals for the occurrence of any of a plurality of predetermined conditions. The memory circuit includes an array of memory cells (each cell storing data determining a value of a breakpoint condition of interest), and selected ones of the cells can be read in response to various combinations of the signal bits. In some embodiments, the array includes 2.sup.N cells and data stored in each cell is readable in response to N binary signal bits which are treated as an N-bit address signal. The memory circuit outputs the accessed data value from one memory cell, which would be used as a breakpoint signal that halts or initiates operation of the circuit originating the signals being monitored.

Abstract: To support load instructions which execute out-of-order with respect to store instructions, a mechanism is implemented to detect (and correct) the occurrences where a load instruction executed prior to a logically prior store instruction, and where the load instruction received data for the location prior to being modified by the store instruction, and the correct data for the load instruction included bytes from the store instruction. Additionally, to execute store instructions out-of-order with respect to load instructions, a mechanism is implemented to keep a store instruction from destroying data that will be used by a logically earlier load instruction. Further, to support load instructions that are executed out-of-order with respect to each other, a mechanism is implemented to insure that any pair of load instructions (which access at least one byte in common) return data consistent with executing the load instructions in order.

Abstract: In a data security system, after completion of writing into a P-ROM, a switching circuit is open to thereby disconnect the connection between an internal bus and an external bus. In this state, it is impossible to read the contents out of the P-ROM. To read the contents, a protection releasing terminal is brought to "H". This causes a switching circuit to conduct to make possible read-out. The "H" signal is simultaneously supplied to an erasion signal generating circuit to erase a part selected by an erasion selecting switch. Secrecy is substantially maintained because a program in the P-ROM is not entirely read. The remainder except the erased portion can undergo checking for correctness of writing.

Abstract: One aspect of the invention relates to a method for detecting synchronization violations in a multiprocessor computer system having a memory location which controls access to a portion of memory shared by the processors, the memory location having at least one lock bit indicating whether the portion of memory is locked by one of the processors and a plurality of bits for storing a data value. The method comprises reading the memory location by an individual processor; testing the lock bit to determine whether the portion of memory is locked; if the portion of memory is not locked; asserting the lock bit to indicate the portion of memory is locked; incrementing the data value to represent a global access count; writing the lock bit and the data value back to the memory location; and incrementing a data value stored in a memory location associated with the individual processor to indicate an individual access count by the individual processor.

Abstract: A testing system selectively activates products of a semiconductor integrated circuit device mounted on a burn-in board, supplies test data signals to the products to see whether or not a defective product is mixed into the products, and a power distributor incorporated in the testing system supplies electric power only to the activated products so that non-activated products do not affect the test data signals.

Abstract: A disk storage control system includes dual controllers having real-time, synchronous, mirrored memory therebetween to provide immediate, accurate, and reliable failover in the event of controller failure. Non-volatile random access memory provides retention of data during a loss of power and during the manipulation of hardware for purposes of repair. A communication path is established within the mirrored memory between the controllers to monitor and coordinate their activities. The state of the mirrored memory is continuously monitored for accuracy of the mirror and failure detection. Concurrent and ready access by a host computer to the same disk storage control data set from each controller is provided without need for extra manipulation or extra direct memory access (DMA) activity to satisfy host requests. Accordingly, either controller can provide immediate and reliable failover control for the disk storage system.

Abstract: In a digital system having non-volatile memory devices for storage of digital information therein, the digital information being organized in sectors, each sector having a data field and a corresponding extension field, a controller device for performing operations such as reading and writing to and erasing information from a selected plurality of sectors and further verifying successful erasure of the selected erased sectors, the controller device including an error detection circuit for detecting errors within each of the sector data fields using the corresponding sector extension field and a flash interface circuit coupled to the non-volatile devices through a data bus for receiving an erased sector of information therethrough and being operative to pass the data field of the erased sector information and a predetermined extension field to the error detection circuit wherein the error detection circuit calculates an extension field corresponding to the erased sector data field, compares the calculated exte

Abstract: In a ring network, a network element having no routing protocol is connected between first and second nodes, and the first node has a link status table indicating link states of the network element and the second node. The first node transmits a health check polling message at periodic intervals to the network element as well as to the second node to elicit responses therefrom, updates each of the link states when no response is returned, examines the link status table at periodic intervals, and broadcasts a message to the network for updating a routing table of a third node of the network so that an alternate route is established from the third node to the network element via the first node if the link status table indicates that there is a faulty condition between the network element and the second node. The third node transmits a network management message to the network element via the alternate route according to the updated routing table.

Abstract: A method and apparatus for verifying the behavior of properties or functions of a system by forming a reduced model for each property of the system, and running a given simulation operation on the reduced model to verify the behavior of each said property. When a property or function does not behave as expected, the system model is adjusted, and only those functions having a property affected by the adjustment are rechecked. In one illustrative embodiment, a system model is reduced by eliminating all variables having no effect on the function or property being checked. The resulting reduced model can be further reduced by adjusting the range of each variable therein to a minimum range necessary to check the behavior of that specific property. If it becomes necessary to change the system model in order to fix a problem relative to one property, then only those properties having a reduced model affected by that change or fix are re-verified.

Abstract: A retrofitted personal computer ("PC") has an access control module attached to the rear wall of the PC. A secondary switch within the access control module is connected in series between the main switch of the PC and the power supply. An authorized user remotely controls the powering of the PC by turning "ON"-"OFF" of the secondary switch through the "ON"-"OFF" radio pre-coded transmitter. The disk drive of the PC is protected by a disk drive lock, which is interconnected with the access control module and the PC by a cable.

Abstract: A method and system for monitoring the use of a rented software program module. A rented software program module is downloaded from an Internet site operated by an authorized software rental service provider along with a Check-in/Check-out module and a Software Monitor module. The Check-in/Check-out module provides required licensing information for the rented software program module to the Software Monitor module. The Software Monitor module monitors use of the rented software program module while it is in use by the user. Particularly, the Software Monitor prevents use of the rented software program module after the expiration of the licensed usage time or licensed number of uses. The Software Monitor prevents unauthorized copying of the software program module. The desired software program module may be rented on a pay-per-use basis.

Abstract: A microcomputer with a flash memory that solves a problem of software overload due to polling during writing or erasing of a flash memory, an interrupt caused by the completion of writing or erasing, or an interrupt caused by a monitor timer. This solution is achieved by suspending the supply of a clock signal from a clock generating circuit to a CPU, and restarting the supply of the clock signal after completion of writing or erasing. This clock signal suspension, in turn, is achieved by providing a NAND gate and an AND gate. The NAND gate NANDs a CPU rewrite mode designating signal and a write/erasure busy signal, both of which are output from a flash control circuit and are kept "1" during writing or erasing of the flash memory, thereby outputting a signal "0" during the writing or erasing. This state fixes the output of the AND gate to "0", which suspends the supply of the clock signal from the clock generator to the CPU.

Abstract: A method for allowing anonymous user login to a computer begins when an application request is received from a client. The next available anonymous user name is determined and assigned to the client's application request. The anonymous user name is authenticated and a new session is created, which invokes the application targeted by the client's application request. When the client terminates execution of the application, the anonymous user name is returned to the anonymous user name pool and is available to be reassigned to the next anonymous user.

Abstract: Upon data access, an attribute-data extraction unit extracts location data and a password from attribute data which is added in advance to subject data to be accessed. At the time of requesting for an access to the data, the extracted password is compared with a password which is inputted from an input unit, and the extracted location data is compared with current location data detected by a location-data detection unit. An access permission unit permits access to the data in accordance with the comparison results obtained by the password comparison unit and the location-data comparison unit. By virtue of the process, it is possible to more strictly protect confidential information in a data processing apparatus.