Abstract: A computer system includes a timer which times out if the operating system does not periodically reset the timer. When the system fails and no longer resets the timer, the timer times out, and the computer is reset. The system performs its power on program and checks the memory array for bad memory blocks, which are mapped out of the memory. Next, the system alerts the operator of the failure using a pager. The system then reboots itself from a hard drive having two separate bootable partitions, one for the operating system in the first partition, and one for a diagnostics program in the second partition, so that an operator may diagnose and remedy the problem. The operator may set an indication of which partition to use for booting. The system further provides for remote access so that the operator may interact with the diagnostics program from a remote location.

Abstract: A method of writing to flash memory cells in a flash memory device. The flash memory device includes a first memory array and a second independent memory array. The first memory array includes memory blocks each having a memory cell. The second independent memory array includes block lock-bits each corresponding to one of the memory blocks. The method of writing to a memory cell in one of the memory blocks of the first memory array includes the steps of issuing a command to write to the memory cell, determining if a corresponding block lock-bit in the second independent memory array is set, and writing to the memory cell if the corresponding block lock-bit is not set.

Abstract: A method of booting a computer system with identifying the type of a CD-ROM disk drive of the computer system, the method comprising the steps of: producing an ATAPI IDENTIFY DRIVE command and outputting the ATAPI IDENTIFY DRIVE command to an IDE controller; reading information memorized in a memory of the CD-ROM disk drive in response to the ATAPI IDENTIFY DRIVE command; comparing the information with a predetermined set of internal CD-ROM disk drive information, and determining the type of the CD-ROM disk drive; and selecting a device driver according to the type of the CD-ROM disk drive, and loading the device driver on a memory.

Abstract: A storage device for use with a computer is provided, the device includes self diagnostics and configuration. The device is adapted to recognize when the host computer system requests an operating system from the device, and instead of providing the operating system, provides its own diagnostic and configuration software. When the software executes on the computer, the software causes a user interface to be generated, which provides various configuration and diagnostic options to a user. Upon termination of the self diagnostic and configuration software, the device provides the operating system to the computer such that the start up sequence is resumed.

Abstract: The program system of a complex computer system is highly customer-specific, for which reason the start-up varies considerably. The start-up system of such a computer system must therefore be very flexible. On the other hand, however, early and close monitoring of the complex start-up should be ensured. These requirements are satisfied by a start-up system which has a start-up table generated off-line.

Abstract: One of processors connected effectively to a system is allocated to a master processor and the other remaining processors are allocated to slave processors. Each processor compares the self processor number of a processor number register and the processor number of the other processor of a processor effective register. For example, when the self processor number is smallest as compared with the other processor numbers, it is recognized that the self processor is a master processor. A master initialization diagnosing process after completion of the allocation is monitored by the slave processor. When an abnormality of the master processor is recognized, a degeneration to disconnect the master processor from the system is executed and is again reconstructed by the allocating process of master/slaves. Even when an abnormality occurs in the master processor, the operation in which the system was degenerated can be executed until the minimum construction in which two or more processors normally operate.

Abstract: A security enhanced computer system arrangement includes a coprocessor and a multiprocessor logic controller inserted into the architecture of a conventional computer system. The coprocessor and multiprocessor logic controller is interposed between the CPU of the conventional computer system to intercept and replace control signals that are passed over certain of the critical control signal lines associated with the CPU. The multiprocessor logic controller arrangement thereby isolates the CPU of the conventional computer system from the remainder of the conventional computer system, permitting separate control over the CPU and separate control over the remainder of the computer system. By controlling the control signals that are normally passed between the CPU and the remainder of the computer system, the multiprocessor logic controller permits the coprocessor to perform highly secure operations.

Abstract: An apparatus for testing the sharing of stored information including a computer-readable storage medium and an information sharing protocol test harness module stored on the computer-readable storage medium. The information sharing protocol test harness module executes an information sharing protocol test case on a computer system responsive to a test initiation input. The information sharing protocol test case tests the locking of storage locations to prevent data corruption responsive to being executed.

Abstract: A method, apparatus and computer program product are provided for verifying integrity of predefined data structures in a computer system. A central software failure map is stored which includes for each of the predefined data structures a corresponding in-flux bit. The corresponding in-flux bit is set in response to a request to update one of the predefined data structures. Then updating of one of the predefined data structures is performed. The corresponding in-flux bit is reset in response to completing the update of the one of the predefined data structures. During recovery, the corresponding in-flux bits are checked to identify any unstable data structures.

Abstract: The detection and removal of viruses from macros is disclosed. A macro virus detection module includes a macro locating and decoding module, a macro virus scanning module, a macro treating module, a file treating module, and a virus information module. The macro locating and decoding module determines whether a targeted file includes a macro, and, where a macro is found, locates and decodes it to produce a decoded macro. The macro virus scanning module accesses the decoded macro and scans it to determine whether it includes any viruses. Unknown macro viruses are detected by the macro virus scanning module by obtaining comparison data that includes sets of instruction identifiers from the virus information module and determining whether the decoded macro includes a combination of suspect instructions which correspond to instruction identifiers. The macro treating module locates suspect instructions in the decoded macro using the comparison data and removes the suspect instructions to produce a treated macro.

Abstract: A method and device of plugging and immediately playing a CPU. The user sets the settings of working frequency and voltage of the CPU through the system firmware of a computer. Then, the system stores the settings in a storage device, and the CPU is reset by a reset unit, thereby the multiple frequency controller and voltage converter take control of the operation to instruct the CPU to determine the working speed by a new multiple frequency ratio and to change the voltage into a working voltage corresponding to the model and brand of the CPU without the use of jumpers or switches. The goal of plugging and immediately playing of a CPU is achieved.

Abstract: This structure is a stand alone or laptop computer that has a detachable hands-free mobile computer housed therein. The stand alone (or laptop) computer and the detachable hands-free mobile computer each can operate independent of or together with the other computer. Also each computer can communicate with the other during operation while connected or disconnected from each other.

Abstract: A data processing system including a first and second host, a first and second outboard file cache connected to the first host, and a first and second secondary storage device connected to the first host. The system operation includes the first host reading file data from the first or second secondary storage device after the data is cached on both the first and second outboard file caches. File data is updated by writing to both first and second outboard file caches. File data is destaged by writing data from the first outboard file cache only, to first and second secondary storage devices. Failure of a single outboard file cache is handled by the first host not reading and writing to the failed outboard file cache. Site-wide failure of first host, first outboard file cache, and first secondary storage device is handled by establishing communication from second host to both second outboard file cache and second secondary storage device and resuming processing.

Abstract: The invention modifies an executing instance (target process) of an arbitrary computer program by replacing the heap manager in the target process. All functions in the process that manipulate dynamic memory are patched with replacement functions that implement improved heap management. The invention is applicable to any computer program that makes use of dynamic (heap) memory. In a second aspect of the invention, the improved heap implementation performs heap error checking in addition to managing heap storage. Alternative embodiments use the invention to improve performance (speed) using fast allocation algorithms, improve space efficiency of the program, or implement tracing of heap activity for debugging purposes.

Abstract: A management frame circuit has a set of inputs coupleable to a management bus for carrying management frames. Upon receiving the management frames from the management bus, the management frame circuit determines whether each of the management frames conforms to a frame template. The management frame circuit then asserts an indication that a management frame is bad, if the management frame is determined to not conform to the frame template. The bad fame indication is later deasserted in response to recognition of a predetermined set of bits on the management bus.

Abstract: A method for providing secure registration and integrity assessment of software in a computer system is disclosed. A secure hash table is created containing a list of secure programs that the user wants to validate prior to execution. The table contains a secure hash value (i.e., a value generated by modification detection code) for each of these programs as originally installed on the computer system. This hash table is stored in protected memory that can only be accessed when the computer system is in system management mode. Following an attempt to execute a secured program, a system management interrupt is generated. An SMI handler then generates a current hash value for the program to be executed. In the event that the current hash value matches the stored hash value, the integrity of the program is guaranteed and it is loaded into memory and executed.

Abstract: A reloading state analyzer for allowing a tree of trigger event sequences to be tracked is presented. The reloading state analyzer provides an input interface for receiving and conditioning input state data. A configuration memory stores configuration structures containing multiple compare terms and associated actions. A tree of configuration structures may be downloaded to the configuration memory from a user interface. The reloading state analyzer compares a plurality of current compare terms with input state data. When the input state data matches one of the current compare terms, an action associated with the matching compare term is executed. The action may be a state collection control action, such as an arm, disarm, trigger, collect or stop collection action, or it may be a reload action. If the action associated with the matching compare term is a reload action, a new set of compare terms are retrieved from the configuration memory and become the current compare terms.

Abstract: A mechanism for providing security functions for an integrated circuit device is provided. In one particular embodiment of the present invention, the integrated circuit device includes an input coupled to a voltage supply. A reference circuit coupled to the input receives a voltage from the voltage supply. The reference circuit is coupled to a security circuit which implements a control function which renders circuits within the integrated circuit electronically inaccessible for a period of time.

Abstract: A data processing system that includes an improved architecture for providing hot spare storage devices. Specifically, the data processing includes a bus that is connected to one or more computer systems and a number of storage subsystems. Each storage subsystem includes storage devices and a controller. The controller in a storage subsystem provides the connection to the bus and an interface for controlling data transfers to and from the storage device. A backup storage system is connected to the bus. The data processing system also includes a detection means for detecting a failure of a storage device within one of the plurality of storage subsystems and a backup means for using the backup storage device to replace the failed storage device.

Abstract: A converter, which may be used for implementing either logarithmic or inverse-logarithmic functions, includes a memory, a multiplier, and an adder. The memory stores a plurality of parameters which are derived using a least squares method to estimate a logarithmic or inverse-logarithmic function over a domain of input values.