Abstract: A computer system monitors inter-process communications and performs a synchronous (global) checkpointing for processes that belong to a checkpoint group. The system also performs a local checkpointing at respectively arbitrary times within each process. When a fault occurs, a validity of each checkpoint is examined in accordance with monitoring results of inter-process communications related to the fault process. If the most recent checkpoint of the fault process is valid, only the fault process is rolled back. If it is invalid, all processes of the checkpoint group are rolled back to the global checkpoint, or each of the processes are rolled back to each optimum (valid) checkpoint.

Abstract: A method and system for implementing a Restart Service for the Object Transaction Service are described. The present invention provides a method and system which trigger restart of an OTS instance upon system recovery or upon system failure. The Restart Service runs independently of the client or server processes which it restarts. When a client or server enters a pending state for a transaction, a permanent record containing information to allow the OTS instance to be restarted is stored in a Restart Repository. In the event of system recovery being needed, or of a system failure, a Restart Daemon reads information from the Restart Repository and recreates the process context. The Recovery Service is initialized and log data replayed to a Transaction Manager to determine the outcome of pending transactions. Failed objects and instances of the OTS are restarted.

Abstract: In a telecommunications system containing more than one host computer and multiple real connections to the telecommunications network, an apparatus, method and system for allowing transmission to the dynamic reassignment of sessions from a failing host to an alternate or backup host computer without requiring changes to the devices or addresses of devices connecting to the host.

Abstract: A disk drive has an error recovery procedure with a plurality of ERP steps. An unused capacity of an alternate area on a disk for reassigning data is determined. While executing the error recovery procedure, an execution condition for reassigning data is changed based unused capacity of the alternate area. Data is reassigned to the alternate area in response to the execution condition. This prevents the early loss of the alternate area.

Abstract: An Array Built-In Self Test (ABIST) circuit places on-chip circuits such as memory arrays in a known state, then stops. In the alternative, the ABIST circuit may initialize to a particular subcycle within a pattern sequence, and repeatedly loop on the subcycle, or repeatedly loop on the entire pattern sequence.

Abstract: A proxy which is part of a firewall program controls exchanges of messages between two application entities. The proxy interrogates attempts to send a communication session by requesting entities with a server entity in accordance with defined authentication procedures. The Proxy interfaces with networking software to direct a communication stack to monitor connection messages to any address on specific ports. The requestor's address, and the server's address are extracted from the messages and checked fo compliance with a security policy such as one including an access control list. If either address is invalid, the proxy deletes the message. If both are valid, the message is relayed, and the ports used are tracked for a predetermined time. Reply messages are then sent using the address of the server entity so that the proxy is transparent to the requester.

Abstract: A lockstep processor system adds error detection, isolation, and recovery logic to one or more lockstep processor system functions; namely, control outputs, processor inputs, I/O busses, memory address busses, and memory data busses.

Abstract: A method for a source to obtain the rights of a target object is disclosed. The source first obtains the rights of a source object, which rights include authorization to access a target object and to modify authentication data of the target object. Next, the source object generates new authentication data. After accessing the target object using the rights of the source object, the source modifies the authentication data of the target object to include the new authentication data. Using the new authentication data, the source obtains the rights of the target object, whereby the source becomes a proxy for the target object. As a proxy, the source uses the rights of the target object. Alternative processes for proxy authentication, as well as apparatus for proxy authentication, are also disclosed.

Abstract: When connection between a computer body and an expansion unit has been detected, a system BIOS detects whether or not a storage device in an access lock state exists in the expansion unit. If a storage device in the access lock state exists, the system BIOS issues APM event to turn on a high-order driver for requiring a user to input a password through the operating system. The system BIOS supplies the input password through the high-order driver to the storage device and returns, to the high-order driver, a result of determination of releasing of the access lock of the storage device. If the result of the determination of releasing is affirmative, assignment of the resource to the storage device is performed.

Abstract: A fault tolerant memory system is disclosed which includes a main memory device, storing data and an associated error detecting code, and a shadow memory device, storing data corresponding to the data stored in the main memory. A multiplexer, selectively couples data from either the main memory device or the shadow memory device to an output terminal in response to a control signal. A controller reads the data and associated error detecting code from the main memory device and the corresponding data from the shadow memory device, and generates the multiplexer control signal such that the multiplexer couples data from the shadow memory device to the output terminal if the data from the main memory device is not the same as the data from the shadow memory device and the error detecting code indicate an error in the data from the main memory device, and otherwise couples the data from the main memory device Lo the output terminal.

Abstract: A method of determining the functionality of a software system includes inputting a test plan to the software system via a software testing interface program, and logging an indication of one or more resulting outputs of the software system compared to expected output(s). The test plan invokes a sequence of test scripts and includes associated parameter inputs for the test scripts, and an expected output of the function or transaction of each test script. The test scripts are selected from a set of test scripts each able, when input to the software system via a software testing interface program, to prompt performance of a transaction or function for which the software system is designed.

Abstract: A fault tolerant computer system is disclosed which uses redundant voting at the hardware clock level to detect and to correct single event upsets (SEU) and other random failures. In one preferred embodiment, the computer (30) includes four or more commercial processing units (CPUs) (32) operating in strict "lock-step" and whose outputs (33, 37) to system memory (46) and system bus (12) are voted by a gate array (50) which may be implemented in a custom integrated circuit (34). A custom memory controller (18) interfaces to the system memory (46) and system bus (12). The data and address (35, 37) at each write to and read from memory (46) within the computer (30) are voted at each CPU clock cycle. A vote status and control circuit (38) "reads" the status of the vote and controls the state of the CPUs using hardware and software. The majority voted signals (35) are used by the agreeing CPUs 32 to continue processing operations without interruption.

Abstract: A method for executing a secure online transaction between a vendor computer and a user computer, wherein the vendor computer and the user computer are interconnected to a computer network such as the Internet for data communications therebetween.

Abstract: The object of the invention is to provide a back-up method for information for setting a system control apparatus by which externally back up data can be used even if version up of or addition of a function to firmware is effected and the back up data can be edited manually.

Abstract: A method of coupling logic devices using spares. A first logic device is coupled to a second logic device using a first plurality of spares. The first logic device is coupled to a third logic device using a second plurality of spares. The second logic device is coupled programmatically to the third logic device by coupling programmatically one of the first plurality of spares to one of the second plurality of spares via the first logic device. The coupling of the first logic device to the second logic device and the coupling of the first logic device to the third logic device comprise coupling a total number of spares not exceeding M(N-1), wherein M is a minimum number of spares that must be coupleable between each potential pair of logic devices in a multiplicity of logic devices, and wherein N is a total number of logic devices in the multiplicity of logic devices.

Abstract: In a computer system comprising first through N-th processors which are provided with first through N-th processor input/output information transmission paths, respectively, an n-th processor is connected to an (n-1)-th processor, an (n-2)-th processor, an (n+1)-th processor, and an (n+2)-th processor, where n represents each of 1 through N, both inclusive. Coupled to the first through the N-th processor input/output information transmission paths and to a system input/output information transmission path for a controlled system, an input/output information path control device connects the system input/output information transmission path to one of the first through the N-th processor input/output information transmission paths.

Abstract: A multi-dimensional node or processor arrangement allows a similar number of nodes in a linear array to be arranged in a more compact form, thus overcoming a latency problem in communications between the most distant nodes/processors. The multi-dimensional arrangement also allows for multiple paths between nodes. This feature greatly improves survivability of the system, such that when one node dies there is always at least one other path that is available to get to the other nodes in the system. Thus, the system can continue to run and only the resources of the one node that died are lost. A first set of routing rules governs the migration of communications between a source node and a destination node around the node array when all of the nodes are functioning. A secondary set of rules displaces or modifies the first set when a node is not functioning.

Abstract: An embedded security processor is used in conjunction with a main processor to provide security for a computer system that is accessible via a computer network. In a preferred embodiment of the present invention, an expansion board is provided that has an embedded security processor dedicated to network communications security tasks. The embedded security processor is controlled by the main processor and intercepts all communications from external untrusted or unverified network systems (i.e., unsecure networks) and verifies that the attempted communication is permissible before allowing the external network communication traffic to access the main processor, or other networked computer resources accessible via a secure network.

Abstract: Apparatus and method for discouraging computer theft. The apparatus and method requires that a password or other unique information be supplied to the computer before the computer BIOS routines can be completely executed. A BIOS memory storing the BIOS routines includes a security routine which will determine whether or not the required password entered by the user, or a known quantity read from an externally connected memory device is present. The security function stored within the BIOS memory also includes an administration function which permits the computer to be either placed in a locked state, thereby requiring password or the known quantity read from an externally connected memory device to be present each time the computer is booted up. The administration function also permits an unlock state which permits the computer boot up process to complete without entering any password or externally supplied quantity.

Abstract: A CPU increments the variation in the corresponding monitor value in a monitor value storage area secured in a RAM, each time an event to be monitored has occurred. When the monitor value must be stored, the CPU adds the incremented one of the variations in the individual monitor values stored in the monitor value storage area to the corresponding value in a monitor value saving area secured in the system area of the disk, executes monitor value saving control by which the monitor value is replaced with the resulting monitor value, and then clears the monitor value storage area.