Abstract: A fault-tolerant computer architecture is described wherein the effect of hardware faults is diminished. The architecture employs a main data bus having a plurality of interface slots for interconnecting conventional computer sub-systems. The number and type of sub-systems may vary considerably, however, a central processor sub-system which encompasses the inventive elements of the invention is always included. The central processor sub-system employs a plurality of central processing modules operating in parallel in a substantially synchronized manner. One of the central processing modules operates as a master central processing module, and is the only module capable of reading data from and writing data to the main data bus. The master central processing module is initially chosen arbitrarily from among the central processing modules.

Abstract: An improvement in protecting information transmitted via a network from illegal copying is disclosed. While data input from an information provider via a network is stored in a storage device, an ID inherent in an information terminal unit stored in a ROM, the time information which is output from a real-time clock counter, an ID of the owner of an ID card read by a card reader are multiplex-recorded as identification information on the input data. Identification information is also multiplex-recorded on the data read from the storage device and to be output through the output terminal.

Abstract: A method for permitting access to secured computer resources based upon a two-piece user verification process. In the disclosed embodiment, the user verification process is carried out during a secure power-up procedure. At some point during the secure power-up procedure, the computer user is required to provide an external token or smart card to the computer system. The token or smart card is used to store an authentication value(s) required to enable secured resources. The computer user is then required to enter a plain text user password. Separate passwords can be used to enable various portions of the computer system. Once entered, a one-way hash function is performed on the user password. The resulting hash value is compared to an authentication value (token value) downloaded from the token. If the two values match, the power-on sequence is completed and access to the computer system and/or secured computer resources is permitted.

Abstract: A method and apparatus for controlling server activation. In the prior art, there exists a race condition between the shutting down of an old server and the starting up of a new server. Further, rapidly restarting servers, such as daemonic servers, are prone to thrashing behavior. However, an embodiment of the invention avoids this undesired behavior by providing an additional "shutting down" state in the server finite state machine running in the ORB daemon. This additional state allows an old server to complete the necessary shut down procedures prior to the startup of a new server. Also, a process is provided for handling servers that are too slow to shut down or start up. A second additional state is provided in the server finite state machine to handle self started servers.

Abstract: A register file backup system for with a computer which processes instructions to generate results which thereby change the visual state of the computer. The computer has a register file with a plurality of addressable locations for storing data. The backup system is adapted to return the visual state of the computer to a previous state if an instruction generates an exception. The backup system utilizes less overhead so as to provide easier register file backup than a comparable software or hardware device. The backup system comprises first means for sequentially storing in program order, address information corresponding to destination locations in the register file where instruction results are to be stored.

Abstract: A recording device which improves a response time to write data by reporting to a host computer the completion of writing operation prior to the completion of writing redundancy data. Data writing command information from the host computer is stored in a command/status memory backed up by a power source in an array controller, and the completion of writing operation is reported to the host computer at the time of the completion of writing updated data prior to the completion of writing redundancy data. Redundancy data is written as a background process. If redundancy data could not be written due to any abnormality of the power source or the like, such redundancy data may be generated from the data in other disk units of the same redundancy group in accordance with writing command information stored in the command/status memory, thereby completing the writing of redundancy data.

Abstract: If no uncorrectable errors are discovered in a received data packet, an acknowledgment is sent back to the sender. Conversely, if the data packet contains uncorrectable errors, no acknowledgment is sent, forcing a re-transmission of that data packet in accordance with an automatic repeat request (ARQ) procedure. In such cases, sets of unquantized signal values relating to received data packets having uncorrectable errors are stored. When two or more sets of unquantized signal values for the same received data packet (as re-transmitted) have been stored, the unquantized signal values are numerically combined on a bit-by-bit basis, and then quantized to regenerate a combined data packet. If no uncorrectable errors are discovered in that combined data packet, an acknowledgment is sent back to the sender. Otherwise, no acknowledgment is sent, forcing another data packet re-transmission.

Abstract: A computing system (10) includes elements (12-24) interfacing at integration points (26-47). One or more of the elements (12-24) may be associated with one or more testing tables. For example, a testing table (48) may include a test procedure (54) and several corresponding test codes (54a, 54b, 54c) associated with alternate product configurations (12a, 12b, 12c) that satisfy the functional requirements of an element (12). The testing tables in the computing system (10) provide a systematic and standardized scheme for defining, creating, modifying, and adapting integration test code. A testing system (11) accesses the testing tables to test the integration of the elements (12-24) in the computing system (10).

Abstract: When an amount of write data instructed by an upper-level system is small, a plurality of disk units are accessed individually and data split in sectors is written therein (Level 5 RAID). When an amount of write data instructed by the upper-level system is large, the plurality of disk units are accessed in parallel and data split in sectors is written therein (Level 3 RAID). When a disk unit in an array, to which a setup instruction is issued according to a processing request sent from the upper-level system, returns a fault reply, an ID management table is used to allocate an auxiliary disk instead of the failing disk unit. After the allocation, data is restored to the replacement disk using the data in normal disk units in the same rank. In a dual-port access configuration, when two transactions access disk units connected to the same port, a deadlock may occur depending on the access procedure.

Abstract: A system and method for preventing contention in a shared memory environment. In one embodiment, a first processor reads a traffic controller which is coupled to a shared memory and to a second processor. The first processor writes its identifier into the traffic controller provided that the traffic controller does not already have an identifier corresponding to the second processor stored therein. If the traffic controller does have an identifier corresponding to the second processor stored therein, the first processor periodically reads the traffic controller until the traffic controller does not have an identifier corresponding to the second processor stored therein. Once the traffic controller has the identifier corresponding to the first processor stored therein, the traffic controller allows the first processor to control access to the shared memory.

Abstract: In an apparatus and method for diagnosing a plurality of disk drives in at least one disk array device, including a disk array control unit which is connected in parallel with a plurality of data storage disk drives, a redundant disk drive and a spare storage disk drive, and which is adapted to access the plurality of disk drives in parallel in response to an access from a host device. The disk array control unit accesses the spare storage disk drive as well as the plurality of data storage disk drives and the redundant storage disk drive, in accordance with a data transfer requirement from the host device, thereby diagnosing the storage disk drive, when the data transfer requirement represents a read transfer or write transfer.

Abstract: A censoring browser method and apparatus are provided for internet viewing. A user profile including user selected censoring parameters is stored. Data packet contents are received and compared with the user selected censoring parameters. Responsive to the comparison, the received data packet contents are processed and selectively displayed responsive to the user selected censoring parameters. The user selected censoring parameters includes user selected censored words and word fragments, and user selected categories. Compared word and word fragments matching user selected censored words and word fragments can be removed and selectively replaced with predefined characters or acceptable substitute words. Tallies of weights for user selected categories are accumulated and compared with used selected threshold values. A predefined message can be displayed responsive to an accumulated tally exceeding a user selected threshold value without displaying the received data packet contents.

Abstract: An apparatus which provides the user with an indication of the computer network's health. The indication is provided by a network management station on the computer network. The network management station has a distributable piece of code which instructs agents to gather diagnostic and status information. The network management station then evaluates the network specific diagnostic and status data gathered by the agents. Based on the evaluation, the network management station generates a representation of the computer network's functionality (i.e., its "health"). Thereby, the user can readily determine whether the computer network requires repairs.

Abstract: A fault tolerant distributed intelligence control system for sensing and control across fault tolerant fiber optic communication media interconnecting a plurality of intelligent nodes. Each intelligent node comprises a digital control and communication processor (DCCP) operating autonomously in relation to DCCPs at other nodes, and a transceiver for interfacing with the communication media. The fiber optic communication media comprises bi-directional serial data buses. The combination provides a low cost highly reliable distributed control system particularly applicable to primary and secondary aircraft control systems, as well as to other vehicle and control systems.

Abstract: A method for programming or testing a CPLD using an additional read register. In one embodiment, the method comprises: instructing the CPLD in one instruction to load program data, load address information and program the program data into a memory location having an address defined by the address information; loading the program data into a first data storage element and the address information into an address storage element; programming the program data into the memory location; instructing the CPLD to read verify data from the memory location; and capturing the verify data into a second data storage element. The second data storage element comprising a read registers. The novel method further comprises comparing the verify data with the program data. The verify data and the program data may be compared within the CPLD or the verify data may be output from the CPLD and compared with the program data externally.

Abstract: According to the invention, a data integrity code including logical block address ("LBA") and circuit implementation are provided. The code and implementing circuitry are utilized to enable data block LBA verification during a block transfer and retrieval process. The preferred data integrity code has embedded LBA information and also serves as a crosscheck code used to detect miscorrection by an error correction code ("ECC"). In a preferred disk drive embodiment, data integrity block ("DIB") is provided to verify that the LBA value associated with a given data block in a host interface matches the value associated with that same data block in a buffer memory and in a data sequencer. In a preferred method of use, data integrity/cross-check redundancy with LBA is appended to data blocks transmitted to a buffer memory and verified after the data block has been transferred from the buffer.

Abstract: A method for supervising the execution of a job in a license restricted environment is disclosed. According to the license restricted environment, some networked machines are licensed for a first type of processing and other machines are licensed for a second (or other) types of processing. In executing a job that requires processing portions or segments of both the first and second types of processing, when the job begins processing the job using the first types of processing on a suitably licensed machine and then fails when attempting to process the job using the second types of processing on the same machine because of a license violation. The method for supervising operates in an automated fashion to detect the stoppage of the job due to license failure and to resume the remaining portions or segments of the job for processing using the second types of processing on a suitably licensed machine.

Abstract: There is provided an information processing device having information processing units between which data can be transferred via a bus provided therebetween. A data requested unit which is one of the information processing units sends an answering signal to a data requesting unit which is another one thereof. The information processing device includes an error detecting part for detecting an error in received data, an answering signal generating part for generating an error answering signal with respect to received data having an error and a normality answering signal with respect to received data having no error, and an information sending part for sending the error answering signal to the bus with priority over the normality answering signal.

Abstract: Automatic shelf-to-shelf address assignment is provided for a plurality of disk drive supporting shelves that are removably contained within a multi--shelf cabinet. Error detection apparatus detects failure in the automatic assignment of shelf addresses. An address input of shelf-N receives a shelf addressing voltage from shelf N+1. Shelf-N checks to ensure that the received shelf-N address voltage is within a correct range. Where-N now increases its shelf-N address by one and applies this incremented address to an address input of shelf-N+1. Accuracy of the shelf-N+1 address input is checked, as are the cable/connectors that connect shelf-N to shelf-N+1. ADC and ADC techniques are used, and operation of the automatic address assignment system is timed.

Abstract: An MxN dynamic spare column replacement memory system for storing M N-bit data words includes a random access memory (RAM) formed by a rectangular array of M rows and N+S columns of single-bit memory cells. Each row has a unique address and stores an N-bit word using a selected set of N of its N+S cells. An N-line parallel data bus provides data access to the DRAM. Responding to a switching instruction from a switch controller at the start of each memory access cycle, a crossbar switch selectively connects each of the N lines of the data bus to a separate one of the N+S columns. Thus during a memory read or write access cycle the N data lines access N cells of an addressed row columns. The remaining S cells of the row are unused. A host computer occasionally checks the DRAM for defective memory cells, and upon finding a defective cell or cells in any row, the host stores the row address and a switching instruction in the switch controller.