Abstract: A power source voltage tracking circuit, for providing a given voltage which is lower than power source voltage, containing a first node for applying a power source voltage, a second node and an output line, a load connected between the first node and the output line to precharge the output line with the given voltage, elements connected between said first node and said second node to charge the second node, and elements to discharges the output line charged with the given voltage in response to the charging voltage of the second node.

Abstract: A First In First Out shift register memory system (10) with a plurality of memory word registers (50) having data inputs connected to a common data-in bus (16), and a plurality of data outputs connected to a common data-out bus (22). A read address ring counter (36) and write address ring counter (32) are responsive to respective read and write pulses to sequentially perform memory read and write operations. A comparator (40) compares the address outputs of the ring counters (36, 32) for equality. A read and a write signal generator (80, 60) are provided for producing respective read and write pulses in response to input transitions of read and write commands. A last operation R/W flip-flop (70) maintains an account of the last read and write memory operation processed by the system.

Abstract: A translation lookaside buffer for caching virtual addresses from a plurality of sources along with the associated physical addresses which physical addresses must be rapidly accessable and in which virtual addresses may appear simultaneously from two of the sources requiring translation into physical addresses, including a primary cache for storing a plurality of individual virtual addresses and associated physical addresses from all of the plurality of sources, apparatus for storing a single virtual address and its associated physical address from one of the plurality of sources which occurs most often each time a virtual address and an associated physical address from that one of the plurality of sources is referenced in the primary cache, and apparatus for ascertaining whether the virtual address held in the apparatus for storing a single virtual address and an associated physical address is a virtual address sought when an attempt is made to access the primary cache for a virtual address from the one of

Abstract: A data processing device comprising a storage circuit accessible by assertion of addresses, an arithmetic logic unit connected to the storage circuit operative to perform an arithmetic operation on data received by the arithmetic unit. Further included is an address register for storing an initial address word indicative of a storage circuit address. An instruction decode and control unit, connected to the storage circuit and having an instruction register operative to hold a program instruction is operative to decode the program instruction into control signals to control the operations of the data processing device and location codes to control data transfers according to predetermined sections of the program instruction wherein at least one of the sections includes a location section selecting the address register and a displacement section containing address data.

Abstract: A multi-task system employs a single interrupt occurring at fixed time intervals to initiate the control functions. The actuator control, servo control and spindle control routines are operated on a priority basis so that if a control function having a high priority is not ready to be executed, the processor immediately performs execution of the next available control function. More particularly, the spindle control process is operated in the foreground with the actuator control and servo control routines operated on an interrupt basis of the spindle control routine. Upon receipt of the interrupt signal, priority is first given to an actuator control routine for execution. Upon completion of the actuator control routine, or if the actuator control is not ready to be executed, access is given to a servo control routine. At the conclusion of the servo control routine, the interrupt exits to the spindle control routine.

Abstract: A semiconductor memory device storing data having a unit of N bits (N is an integer) includes M memory elements (M is an integer and larger than N) each divided into a plurality of blocks each having a plurality of memory cells each storing one-bit data, and M internal bus lines each carrying one-bit data and connected to a corresponding one of the M memory elements. A designating circuit receives an address signal from an external device and designates one of the plurality of blocks of each of the M memory elements so that M blocks are designated by the address signal. A ROM stores information on whether or not each of the plurality of blocks of each of the M memory elements has a defective memory cell and outputs the information in accordance with the address signal. N external bus lines individually carry one-bit data.

Abstract: Apparatus for providing a boundary between on-board CPU memory and slot bus (EMS) memory is disclosed. A programmable comparator compares the CPU address with a pre-determined address in order to permit the memory array to be accessed by the CPU address or the EMS register, thus preventing the same memory array from being accessed by both the CPU address and the EMS register.

Abstract: A predetermined number of logical page addresses are effectively translated into corresponding real ones. The number of the logical page addresses is determined by (M+N) bits and, each of the logical page addresses includes upper M-bit and lower N-bit. Logical page address registers, whose number is equal to 2.sup.N, are provided to respectively store the predetermined number of logical page addresses applied. Address translation buffers (whose number is also equal to 2.sup.N) each stores 2.sup.M real page addresses which are grouped according to each of the lower N bits. The address translation buffers receive the upper M-bit of one of the logical page addresses, and output real addresses. An address translation controller receives the outputs of the address translation buffers and also receives the lower N-bit, and selects the real page addresses using the lower N-bit. The selected real page addresses are applied to a plurality of real address registers.

Abstract: A coherent coupled memory multiprocessor computer system that includes a plurality of processor modules (11a, 11b . . . ), a global interconnect (13), an optional global memory (15) and an input/output subsystem (17,19) is disclosed. Each processor module (11a, 11b . . . ) includes: a processor (21); cache memory (23); cache memory controller logic (22); coupled memory (25); coupled memory control logic (24); and a global interconnect interface (27). Coupled memory (25) associated with a specific processor (21), like global memory (15), is available to other processors (21). Coherency between data stored in coupled (or global) memory and similar data replicated in cache memory is maintained by either a write-through or a write-back cache coherency management protocol. The selected protocol is implemented in hardware, i.e., logic, form, preferably incorporated in the coupled memory control logic (24) and in the cache memory controller logic (22).

Abstract: An processing system having a disk storage unit which acts as physical RAM storage. A disk controller, disk and small RAM unit are controlled by a separate CPU and MMU using a virtual memory scheme. This assembly is connected to a set of processing nodes by way of a bus, such that each of the nodes can access the memory directly through the MMU as virtual memory. The CPU controls the transfer of data to and from the disk as it is requested from the nodes. The nodes may then proceed to process the image data without any interaction with the host system.

Abstract: An instruction fetching device includes one or both of a cache device and a branch history table. The cache device stores a plurality of pairs, each pair including an instruction string divided into minimum unit instructions and an address of the instruction string. At the time of reading an instruction, an instruction string is selected and output by every minimum unit instruction from at least two pairs. The branch history table stores a plurality of pairs, each pair including a branch destination address and a set of an address of a branch instruction and a value obtained by subtracting a given value from the address.

Abstract: Virtual address space for array data to be stored in a virtual memory is allocated by establishing a table that associates segments of the virtual address space with predetermined array data dimensions and maintaining a map that identifies, for each segment, which portions of the segment have been allocated to store array data. The table and map are used to identify a contiguous portion of the virtual address space for the array data to be stored.

Abstract: An improvement in a microprocessor permitting the selection of write-back, write-through or write-once protocols is disclosed. A pin is connected to either ground or Vcc potential to select either the write-through or write-back protocols. When this pin is connected to the read/write line, the write-once protocol is selected. Interconnection between two processors is described which permits the processors to operate in a write-once protocol with a minimum of glue logic.

Abstract: A computer implemented method for minimizing the grant of pages locks and the number of outstanding locks while ensuring consistency of the copies of pages resident among a first, and a second data cache with the original pages in shared external storage. A first processor requesting a lock on a designated page is granted a lock over the group of pages including the designated page in the absence of a concurrent lock to the page or group held by another processor. Any changed page is copied through to external storage. Otherwise, a processor intending to alter a page causes a global lock manager to notify concurrent lock holders, invalidate copies of the page in their local caches, and obtain an exclusive lock to the requesting process for the duration of its operation on the page. After this the lock is demoted to share and the changed page also copied through to external storage.

Abstract: An improved method for accessing memory in a computer system using standard fast paged mode memory access for a second memory access where the second memory access is pending at the completion of a first memory access. However, if at the completion of a first memory access there is no pending memory request, the RAS line of the memory is deactivated allowing precharge during an idle state on the bus.

Abstract: Apparatus for decoding and comparing memory addresses which determines DRAM size and interleave options utilized is disclosed. A row address and bank select bits are decoded and latched and are subsequently compared with the address during the next memory cycle. If the next address matches the address stored in the latch, a "page hit" occurs and the memory cycle is shortened since the addresses during the consecutive memory address will differ only in the column address.

Abstract: A facility is provided for locating a file in a backup memory, in which each of the components forming a hierarchical pathname identifying the file is converted into a unique identity using a minimum of bytes, and in which the location of the file in backup memory is determined as a function of each such identity rather than the component names forming the hierarchical pathname.

Abstract: An address bus control system is provided of the type in which a controller including a central processing unit is connected through an address bus and a data bus to hardware modules which control equipment to be controlled. An address space defined by an address bus includes a discrimination space for discriminating the attribute of the hardware module and a function space for allocating and clearing an address space for a function interface of the hardware module. The attribute of a hardware module connected to a connector having a corresponding address is recognized using the discrimination space. The function interface of each hardware module is assigned a space within the function space in accordance with the contents of the discrimination space in concern, or the assigned space is canceled.

Abstract: A selection circuit for a bipolar ECL memory having memory cell connected to cell selection lines and, more particularly, to upper and lower wordlines. The circuit includes a line driver connected to the upper wordline, an input stage for controlling the line driver to activate the upper wordline connected thereto in response to an address signal, and a switching device responsive to the input stage for applying a discharging current to the lower word line to speed up deactivation of the memory cell in response to a change in the address signal. In one embodiment, the line driver is also turned on at an increased rate for a limited time following application of the address signal to speed up the activation of the line.

Abstract: The effective capacity of an instruction cache in a digital signal processor with a modified HARVARD architecture is enhanced by decoding a current instruction to be executed to determine whether it is a program memory data access (PMDA) instruction that requires a data transfer from the program memory when the next instruction is fetched from the program memory. If it is a PMDA instruction, the next instruction is loaded into a cache, which then provides the stored instruction each time the PMDA instruction reappears. This relieves a bottleneck resulting from a simultaneous call for both the next instruction, and datum for the current instruction, from the program memory. The cache is used only for an instruction following a PMDA instruction, and can thus have a substantially smaller capacity than previously.