Abstract: The invention comprises an interface for switching control of a memory management unit (MMU) between a central processing unit (CPU) having a register stack for storing data, and one or more coprocessors (COP) each having register stacks for storing data. The COP is operative when actuated to perform selected functions, not normally performed by the CPU, utilizing information in memory.

Abstract: A method for retransmitting selected data elements read from a memory. A first sequence of individually addressable data elements d.sub.1, d.sub.2, . . . , d.sub.n are read from the memory. First and second signals indicate whether each data element was read without or with, respectively, a transmission error. A second sequence of data elements d.sub.i, d.sub.i+1, . . . , d.sub.n, where d.sub.i is the first data element of the first sequence to have a transmission error is then retransmitted.

Abstract: A virtual memory unit has a plurality of directory and buffer store levels for storing page descriptor information. The memory directories and a least recently used (LRU) device constructed from the same type of standard cache address directory part include parity error detection circuits. The virtual memory unit further includes a state machine for defining sequential states used in generating control signals for directing the memory unit's operation in translating virtual addresses into physical addresses. Programmable control circuits which generate the required input data and control signals applied to the directories and LRU device for reading and updating their contents further include the retry facilities which, in response to certain types of error situations, alter state machine sequencing to again try the virtual to physical address translation with a fresh copy and the LRU replacement operations in a way to improve robustness.

Abstract: An address couple associateive memory (ACAM) for a processor in a chip package provides a first address couple (ACL) CAM and a second absolute address list (AAL) CAM. An associated control unit guarantees coherency of word data in a cache RAM and main memory by indicating the invalidity or validity of each location of address data in the first CAM (ACL) and second CAM (AAL). Each loaction of data words in the cache RAM is associated with a corresponding location in the first (ACL) CAM and in the second (AAL) CAM. Address translation is provided in one clock cycle when writing to a location in main memory specified by a logical address couple.

Abstract: A cache memory is arranged using write buffering circuitry. This cache memory arrangement comprises a Random Access Memory (RAM) array for memory storage operated under the control of a control circuit which receives input signals representing address information, write control signals, and write cancel signals. At least one address register buffer is coupled to the address input of the RAM, while at least one data register buffer is coupled to the data input of the RAM. Thus, in accordance with the present invention, addresses to be accessed in the RAM, as well as data to be written to the RAM, are buffered prior to being coupled to the RAM. As a result, systems utilizing the cache memory arrangement of the present invention need not stall or delay the output of information toward the RAM in order to check for a cache hit or miss. Such determinations can advantageously be made while the relevant address and data are in the register buffers en route to the RAM.

Abstract: A protected method of fast writing of information for at least one mass memory apparatus (DMM.sub.1) belonging to an information processing system including at least one central host (H.sub.1, H.sub.2), two control units (UC.sub.1, UC.sub.2) with independent electrical power supplies (ALIM.sub.1, ALIM.sub.2, BAT.sub.1, BAT.sub.2) connected to a first and second parallel bus (B.sub.1, B.sub.2) is disclosed wherein the method is characterized in that, if the host (H.sub.1, H.sub.2) is connected to each of the two buses via at least one first host adaptor (HA.sub.1, HA.sub.2) belonging to the first control unit (UC.sub.1, UC.sub.2) and the mass memory (D.sub.1 -D.sub.5) is connected to each of the two buses via a first and a second mass memory adaptor (DA.sub.1, DA.sub.2) belonging to the first and second control unit, respectively, which include a first and a second memory buffer (MTD.sub.1, MTD.sub.2), respectively,I--the block of data to be written is memorized in the first host buffer (MTH.sub.1, MTH.sub.

Abstract: Methods and apparatus for optimizing prefetch caching for sets of disc drives with reverse ordered logical block mapping.

Abstract: Apparatus, and accompanying methods for use therein, for translating virtual page addresses in one address space, e.g. virtual, to page addresses in a second address space, e.g. real, and specifically for increasing the speed of such translations by translating multiple contiguous virtual page addresses upon the occurrence of a miss in a translation lookaside buffer (TLB). In response to a TLB miss, the address of each virtual page in a pre-defined block of, e.g. four, contiguous virtual pages, is separately translated through segment and/or page table lookup operations to yield corresponding page frame addresses. The virtual and corresponding page frame addresses for this block are then stored within a single TLB entry.

Abstract: A bus width control circuit being arranged between a first bus and a second bus both of n-bits width, and comprising a buffer group being connected to the first bus and which split data of n-bits into partial data of m-bits and buffer them, a selector which connects each buffer to the second bus in parallel in the case where the effective data bus width of the second bus is n bits and which connects each buffer to a predetermined m bits of the second bus in the case where the effective data bus width of the second bus is m bits, and a control circuits thereof, and a control circuit which locates intact the n-bits data of the first bus in the second bus or by splitting it into partial data of m-bits in a predetermined portion of n-bits data and outputs them sequentially to the second bus, or which splits the n-bits data of the second bus into partial data of m-bits and buffers them in each buffer and then simultaneously outputs them to the first bus, or which sequentially buffers data whose m bits alone of the

Abstract: A multiprocessor system in which a single operating system is controlled by a number of central processing units. The system allows the expansion of its virtual memory without major modifications the operating system. The system utilizes two virtual memories, one with a larger memory capacity than the other. Each memory is controlled by a space control section, which, in turn, is connected to an associated central processing unit. A first program is executed by both space control sections, while a second program is operated by only one of the space control sections. The second program is stored in the second virtual memory, in an area of the second virtual memory not overlapping the area of the first virtual memory.

Abstract: The toroidal computer memory system utilizes toroidal memory paths in its chitecture to enable memory locations along those paths to be obtained in a single access, as compared to multiple accesses typically required by conventional linear computer memory. The storage/retrievable media is designed to replicate paths on the surface of a torus. By defining certain parameters and the mathematical properties of these memory paths in the electronics of a controller, points on the memory paths can be accessed from the storage/retrieval media more efficiently than conventional computer memory.

Abstract: Methods and apparatus for translating a physical address to a logical address for use with a processor which includes an on-chip memory management unit. The apparatus includes an address capture circuit which is responsive to information on the processor bus during table searches by the memory management unit for determining logical addresses. A table address is subtracted from a table access address to provide a portion of the logical address during each level of the table search. The logical address portions are combined to provide the complete logical address. The logical address is stored in a map RAM and is accessed when the physical address is requested by the memory management unit. The logical address and corresponding data and status fields are simultaneously provided to an analyzer unit. The apparatus utilizes a pipeline structure for high speed operation.

Abstract: An address translation mechanism for generating real addresses, within a page. based on stride from a beginning translated address in the page. However, whenever there is a page crossing, an address must go to either the directory look aside table (DLAT) or buffer control element (BCE) to translate a virtual page-address to a real page-address. To avoid the delay this usually causes, the address translation request is sent out before the address is actually needed. This is done by predicting the next page-crossing while real addresses with the current page are being generated based on the stride value. The prediction is based on the stride value, operand size, and page mode.

Abstract: A shared-buffer-memory-based asynchronous transfer mode (ATM) switch module (1) is duplicated (2) and operates in active-standby mode for fault-tolerance. Following failure and repair of a module, contents of the two modules are resynchronized as follows. When the synchronizing operation is begun contents of the memory of the repaired standby module are cleared, all writes to the active module's memory are also made to the standby module's memory, and the system monitors the overwriting of the contents of the active module's memory that existed at the time the synchronizing commences. This is done by a function (FIG. 4), which sets a flat (64) in a queue-length-counter monitor (60) for every active-module queue-length counter (200) that reaches a count of zero, to indicate that its corresponding buffer-memory queue (100) has been emptied.

Abstract: A semiconductor memory device includes a memory cell array block (1; MB1 to MB16) having a first column group (area I) and a second column group (area II). The device also includes sense amplifiers (10-1, 10-2, 10-3 . . . ) provided for each column to detect and amplify a read-out voltage on associated columns. The device further includes a control circuit (20) for activating the sense amplifiers for the first column group and the sense amplifiers for the second column group at different timings to reduce peak current in sensing operation. The control circuit operates in response to a column designating signal to activate first the sense amplifiers for the column group including a column connecting thereto a selected memory cell. The column designating signal includes an externally applied column address bit. The column address bit is supplied to the device simultaneous with row address bits in an address multiplexing memory device.

Abstract: A spare memory arrangement in which a defective chip in a memory array can be electronically replaced with a spare chip of identical construction. A defective memory chip is first detected and located by a suitable means, such as an error correction code (ECC), check sum, or parity check. A sparer chip is constructed to be actuated upon a read to the defective memory chip to replace the defective chip with a memory spare chip. The sparer chip includes a cross-point memory (CPM) cell having an address register for receiving data from a central processing unit (CPU) and routing the data to and from the spare memory chip. The cross-point memory (CPM) cell is actuated by control input from the (CPU).

Abstract: A memory chip, comprising a chip memory section organized to hold a plurality of separate blocks of data, with each of the data blocks containing M individual data units; a circuit for addressing a given block of data in the chip memory section; and an N data unit chip parallel output interface from the memory chip where N is less than M, and N is greater than one. The memory chip further comprises a chip register for receiving from the chip memory section at least a portion of an addressed block of data, which portion comprises P data units, where P is greater than N, the chip register having P register stages for holding the P data units of the addressed data block, wherein the P register stages are grouped into at least a first and second groups of stages, with no group of stages comprising more than N register stages and with at least one of the groups of register stages having a plurality of stages.

Abstract: A buffer memory device comprising memory locations for successively storing successive groups of data units, the successive groups being presented during successive phases, the data units in each group having different buffer periods which are recurrent for all groups. A modulo address generator generates, for each group of data units, a series of addresses for selected locations in a memory wherein the data units will be stored, there being logic address intervals between the successive addresses in the relevant series which correspond to the buffer periods of the respective data units. In every two successive series the memory addresses are shifted by one address interval unit with respect to each other. An efficient data occupation of the memory can thus be realized with simple addressing, since the write addresses during any phase can be used as the read addresses for already stored data units. The buffer device can be used as an interleaver or de interleaver for error correction in CD apparatus.

Abstract: An audio/video data reproducing apparatus reads out data from a first storage, which has its storage area equally divided into clusters and stores audio/video data on a cluster-by-cluster basis, to transfer the data read out to utility equipment over a communication path. A second storage stores address data designating clusters of the first storage. Clusters including data to be read out are searched for, and the address data designating the clusters thus searched for is stored in the second storage in a predetermined order. The address data is then sequentially read out from the second storage to generate a real address addressing a storage location of the storage area, which is in turn provided with the real address to develop the stored data in the predetermined order. In response to an error occurring during the transmission on the communication path, the second storage is interrupted from developing the address data therefrom.

Abstract: A queue structure is functionally equivalent to individual FIFO bank queues but requires only slightly more hardware than the single BSM queue approach. The queue structure uses "self-advancing" WAITING queues (one per BSM) in which there is a one-to-one correspondence between a (valid) queue position and a busy bank within a given BSM. However, the position/bank relationship is dynamically managed such that positions only exist for busy banks, thereby essentially providing a FIFO queue per bank while maintaining one queue per BSM.