Abstract: A integrated mass memory device is formed by combining a piezoelectric bimorph cantilever (214) with a recording surface (212) having a number of storage locations to and from which digital information is transferred using a scanning tunneling microscope or an atomic force microscope mode of operation. Controls circuits (240) are provided for controlling the scanning of the recording surface (212) and for writing and reading information into and from the recording surface. An image storage system stores images captured from an optical sensor using piezoelectric bimorph cantilevers for reading and writing digital information on recording surfaces.

Abstract: An apparatus for extending the memory of an electronic data processing system and a method for providing access to the extended memory for reading data, writing data, and refreshing data. The method provides a partitioning of the original virtual address space into a reduced virtual address space and an extended real memory address space. An extended address register is loaded initially with an extended memory control word by the operating system, but this word may not be changed again until the current process is over. If this control word is changed, it is changed by the operating system such that the use of the extended memory is transparent to the application processes using the system. The method further provides for refreshing of the memory circuitry of the extended memory. The apparatus supports the extended real memory address space by decoding the read and write accesses to the extended real address space, and by providing electrical connections for the refreshing of the extended memory circuitry.

Abstract: A pipelined CPU executing instructions of variable length, and referencing memory using various data widths. A writeback cache is used (instead of writethrough) in a hierarchical cache arrangement, and writeback is allowed to proceed even though other accesses are suppressed due to queues being full. Separate queues are provided for the return data from memory and cache invalidates, yet the order or bus transactions is maintained by a pointer arrangement. The bus protocol used by the CPU to communicate with the system bus is of the pended type, with transactions on the bus identified by an ID field specifying the originator, and arbitration for bus grant goes one simultaneously with address/data transactions on the bus.

Abstract: A content addressable memory comprising a Random Access Memory (RAM) including a plurality of data storage locations. Each of the data storage locations has a unique address. The content addressable memory operates to store a data entry comprising predetermined match information for at least a portion of a data entity. Each at least a portion of a data entity comprises the unique address of the respective data storage location. The RAM has an address port for input of at least a portion of a data entity as an address and an output for outputting the stored data entries. The RAM operates to fetch the data entry stored at the input address and to output the stored match information corresponding to the at least a portion of a data entity, in response to input of the at least a portion of a data entity as an address to the RAM. In a particular embodiment, the RAM comprises an array of RAMs, wherein that at least a portion of a data entity is segmented into n slices.

Abstract: A bit decoder for a memory array includes a decode NOR/OR circuit coupled to an output driver circuit. The decode NOR/OR circuit includes a plurality of input signals connected to respective input FET's all of which are connected in parallel between a common source and a common drain node. One input is also connected to an active pullup FET which is connected in series with the input FET's at the common drain node and which is always maintained slightly on. A bipolar transistor pulls down the common drain node and a bleeder FET pulls down the common source node. The output driver is a BICMOS circuit that provides both the bit selection and bit refresh signals which are of opposite phase.

Abstract: A memory system (10) utilizes miss caching by incorporating a small fully-associative miss cache (42) between a cache (18 or 20) and second-level cache (26). Misses in the cache (18 or 20) that hit in the miss cache have only a one cycle miss penalty, as opposed to a many cycle miss penalty without the miss cache (42). Victim caching is an improvement to miss caching that loads a small, fully associative cache (52) with the victim of a miss and not the requested line. Small victim caches (52) of 1 to 4 entries are even more effective at removing conflict misses than miss caching. Stream buffers (62) prefetch cache lines starting at a cache miss address. The prefetched data is placed in the buffer (62) and not in the cache (18 or 20). Stream buffers (62) are useful in removing capacity and compulsory cache misses, as well as some instruction cache misses. Stream buffers (62) are more effective than previously investigated prefetch techniques when the next slower level in the memory hierarchy is pipelined.

Abstract: In a data processing system, apparatus and method for controlling the type of processing to which data signal groups can be subjected includes a page table entry format having a multiplicity of field positions for storing signals defining page access rights. In addition to the read/write access control, the signal group access rights can be determined by the current mode of operation of the data processing unit and the intended activity of the addressed instruction or data element (i.e., read, write or execute).

Abstract: A fault-tolerant computer system employs multiple identical CPUs executing the same instruction stream, each with their own independent memory. The multiple CPUs are loosely synchronized, as by counting events such as operating cycles and stalling any CPU ahead of others. Data output references via separate busses are voted at separate ports of each of the CPUs by voting circuits which detect when all CPUs have made the same reference, and only then pass on identical references to external I/O busses. The ports may include FIFO buffers to allow output references from the asynchronous CPUs to be handled as the CPUs load the FIFOs at different times. Input data to the CPUs from the I/O busses is not voted, but is buffered to allow the CPUs to accept it at their own clock rate.

Abstract: A system for reducing purging of a translation lookaside buffer (TLB) to reduce operating system overhead in a system running multiple levels of virtual machines. A system typically must purge TLB entries whenever an underlying page table entry is invalidated due to paging activity on the host machine, or an underlying guest machine. A system for reducing the number of cases in which guest translations are based on host page table entries is provided. Additional logic is supplied to analyze each invalidate page table entry (IPTE) instruction to minimize the extent of purging required as a result of that instruction. When the region relocate facility is in operation, or when no pageable TLB's have been constructed, only the entry corresponding to the page table entry to be invalidated need be purged. This limited purging reduces the overhead by reducing the time spent in purging and the time required in address translation to rebuild the TLB.

Abstract: This dynamic random access memory having a plurality of rated voltages as an operation supply voltage operates accurately with a sufficient operating margin for each rated voltage. The dynamic random access memory comprises a circuit (200; 120, 130) for generating a signal for defining operation speed/timing of a sense amplifier (50) depending on the operation supply voltage, and a circuit (210) for driving the sense amplifier in response to an output of a defining signal generating circuit. The sense amplifier driving circuit comprises a first gate (G1) for transmitting a sense amplifier activating signal as it is in response to the defining signal, a second gate (G2) for passing therethrough a sense amplifier activating signal passed through a delay circuit (100) in response to the defining signal, and transistors (25, 25'; 25) for driving the sense amplifier in response to outputs of the first and second gates. One of the first and second gates is activated by the defining signal.

Abstract: A DMA controller for supporting a data transfer operation between a first memory and a second memory includes a selector for selecting data stored in the first memory per data unit, a shifting circuit for shifting the data selected by the selector to one direction of required numbers, a F/F (flip-flop) for storing the data shifted by the shifting circuit for every data unit, a feedback circuit for feedback of the stored data by the F/F to the shifting circuit, and a transfer circuit for transferring the data stored in the F/F to the second memory.

Abstract: A hierarchical memory which includes a backing store read/write memory (18) for storing first words, and a read-only memory RAM (60) for storing frequently used words. The buffer store has two parts, a cache RAM (64) and a two-word queue (62) comprised of two fetch buffers. The cache RAM is provided for storing a copy of some of the word stored in the backing store in accordance with a use algorithm. The ROM, queue buffers and cache RAM are simultaneously searched to see if the address for requested words is in either of them. If not, a fetch (76) is made of the backing store (18) and the words are written into the fetch buffers. The next time that address is presented, the fetch buffers are written into the cache and simultaneously read out to the bus. A first Y-mux (63) is provided between the ROM and the cache RAM for multiplexing the appropriate ROM columns to drive the Cache RAM bit lines directly when an internal micro-address is selected.

Abstract: A method for utilizing computer memory devices when they have compressed data is disclosed. Specifically, the techniques focus on the field of operating devices so as to access randomly specified portions of such compressed data. It has particular applicability in computer tape drives such as are used in computer peripheral memory backup devices. These improved methods act to efficiently ascertain the location of the desired data with a minimum amount of effort. One embodiment of the present invention comprises the use of records which represent a number of files or an amount of data stored. Each record is independently compressed to allow independent access and uncompression. The records may include labels for identification purposes. Each label is typically an uncompressed value or series of values stored at the front of each record. Additionally, offsets are specified in labels to indicate the distance from the beginning of the first record to any item of data.

Abstract: A DMA control device (10) is connected with an n-bit address bus (12) by way of a bidirectional internal n-bit bus (14). The m most significant bits of signals received on the bidirectional bus (14) are reserved for carrying codes which identify or enable the DMA device to respond, to generate a load signal, to generate a count signal, and to generate an output signal. The remaining bits are reserved for address data. The load signal causes the remaining bit addresses to be loaded into counters (22) or registers (40). The count signal causes the counters (22) or a latched incrementor (44) to increment. The output signal controls three-state buffers (24, 42, 46) which cause the current address to be outputted on the bidirectional bus. In this manner, the DMA control device has only a single bus and in the embodiment of FIG. 2 replaces the counter array with a register array.

Abstract: A microprocessor consists of an arithmetic section for executing arithmetic processing with a program, a holding circuit for holding a designated address AD1 at which a piece of data DA1 is stored in an external memory, and a signal generating circuit for generating a signal when the designated address AD1 transmitted from the arithmetic section to the external memory is detected.

Abstract: A microcomputer includes a central processing unit (CPU) and an electrically erasable and programmable nonvolatile memory (EEPROM) fabricated on a single semiconductor chip. When CPU issues a data write request to EEPROM, a data write control circuit is initiated to perform a data write-processing in which data in an address of EEPROM selected by CPU is first erased and thereafter data from CPU is written into that selected address. There is further provided an over-written detection circuit for detecting that CPU issues another data write request to EEPROM while the data write control circuit is performing the data write-processing and for producing an over-write detection signal to CPU.

Abstract: A data transfer interface module comprises a storage zone constituted by a plurality of locations referenced by addresses provided by an address generator and serving to acquire a set of data items constituting a block of a size that may be variable, which data items are stored successively in the plurality locations; a control signal COM via control circuit and an acquisition and recording circuit to enable address generation and also loading in the storage zone, the same control circuit in association with a read and transmission circuit then enabling the data to be transmitted, with the data items being extracted one by one from the locations, such that the first item to be transmitted is the last item to have been recorded; and a monitor circuit controlled by the address generator and serving to verify that the number Do of data items transmitted is equal to the number Di of data items acquired and to provide a status word ST which can be read to provide information about proper transmission.

Abstract: A slave controller which provides the control signals for effecting the r and write operation of a memory electrically connected to the VERSA MODULE EUROPE bus (VMEbus). The slave controller comprises a programmable array logic device which receives control and address modifier signals from the data transfer bus within the VMEbus and an address enable signal from a decoding circuit. The decoding circuit, in turn, provides the address enable signal to the programmable array logic device in response to an address strobe signal supplied to the decoding circuit by the data transfer bus. The programmable array logic device being responsive to the control, address modifier and address enable signals enables the memory which for a read or write operation. The programmable array logic device next provides a write pulse to the memory when data is to be written into the memory at an address provided by the VMEbus.

Abstract: A data processor of this invention capable of extending the expressible range of constant data in which a portion of the expressible range not necessary for an instruction is removed from that range and the vacancy thus made is utilized for extending the range of data necessary for the instruction.

Abstract: The present invention includes two variations of an apparatus which generate a version of the IORC* bus signal that is supplied to the read strobe input of a floppy disk controller that is asserted at the appropriate time during verify cycles between the floppy disk controller and a DMA controller. These designs allow an 82077 floppy disk controller to operate properly in FIFO mode when it is being used with software that does not require generation of this signal. The designs include use of a PAL and certain bus signal inputs to generate a signal which is asserted at the appropriate times during verify transfers. This signal is combined with the regular IORC* bus signal to produce the signal that is provided to the read strobe input of the floppy disk controller.