Abstract: A least recently used cache replacement system in which the data cache is logically partitioned into two separate sections, demand and prefetch. A cache directory table and a least recently used table are used to maintain the cache. When a new demand data page is added to the cache, a most recently used (MRU) pointer is updated and points to this new page. When a prefetch page is added to the cache, the least recently used pointer of the demand section is updated with its backward pointer pointing to this new page. A cache hit on a demand of prefetch page moves that page to the top of the least recently used table. When a free page is needed in the cache, it is selected from the demand or prefetch sections of the memory based on a comparison of the demand hit density and the prefetch hit density so to maintain a balance between these two hit densities.

Abstract: A memory management arrangement facilitates interprocess data transfers by eliminating the need to construct temporary mapping tables when performing the data transfer operation. The arrangement includes the use of multiple and concurrent mapping tables in conjunction with the transmission of mapping table indentification bits with each data transfer operation.

Abstract: In a multiprocessor data processing unit, a data element in the main memory unit, that has system wide significance, can have a requirement that this data element be altered in a controlled manner. Because other data processing units can have access to this data element, the alteration of the data element must be synchronized so the other data processing units are not in the process of altering the same data element simultaneously. The present invention includes an instruction that acquires access to an interlock signal in the main memory unit and initiates an interlock in the main memory unit, thereby excluding other data processing units from gaining access to the interlock signal simultaneously. The instruction causes the data element related to the interlock signal to be transferred to the data processing unit where the data element is saved, can be entered in mask apparatus and then have a quantity added thereto.

Abstract: A MOS fuse with oxide breakdown based on a MOS cell electrically programmable by tunnel effect and storage of charges at a gate. This cell is converted into a fuse by providing for the application, when the fuse has to break down, of an intense field, greater than the oxide breakdown threshold, in the tunnel window. Thus, the breakdown is irreversible. The disclosed device can be applied notably to fuses designed for the integrated circuits of memory cards.

Abstract: A direct memory access controller including apparatus for storing an address to which information is to be written or from which information is to be read, apparatus for storing data related to the address, apparatus for storing a value indicative of a width of a block of data to be transferred, apparatus for storing a value indicative of a total amount of information to be transferred, apparatus for storing a value indicating a number of addresses to be bypassed during a transfer, apparatus for incrementing the address while decrementing the value indicative of the width of the block and the value indicative of the total amount of information to be transferred until the width of the block has been crossed, and apparatus for changing the address by the value indicating a number of addresses to be bypassed during a transfer when the width of the block has been crossed, and apparatus for resetting the value indicative of a width of a block of data to be transferred to the original value when the width of the bl

Abstract: A system is provided for management of data in cache memories in a multiprocessor environment which allows portions of lines to be valid and exclusive, while other portions are valid, but not exclusive, or invalid. A processor may store into portions of a line under its exclusive control without invalidating copies of the line held in the cache memories of the other processors. The system includes at least two processors, a shared main memory and a system control element, and each processor has a corresponding cache memory, a modified line stack and a sectored line directory. The modified line stack identifies data lines which have been changed since being made resident in cache memory. It also identifies the status of change of each word within those lines. A "shared exclusive" flag in the system control element identifies each line for which portions of the line are under exclusive control of more than one processor.

Abstract: Apparatus for improving the efficiency of computer instructions which transfer data from memory to machine registers and from machine registers to memory. The difficulty arises because such instructions may require data transfers of a variable number of bytes, may involve transfer across word boundaries within memory, and may use a number of machine registers. These features are important to programs which process variable amounts of data at different storage locations. Such transfer operations are performed by "mini-instructions", which are a proper subset of instructions that already exist within the current repertoire. However, the "mini-instructions" used are limited in the use of variables to only those which make most effective use of the hardware architecture. One or more "mini-instructions" must be used to execute the actual software instruction. Because the mini-instructions needed are a proper subset of the actual software instruction, little additional hardware is required.

Abstract: This invention relates to a personal computer having enhanced memory access capabilities, a memory element enabling such enhancement, and a method of operation of a personal computer. The invention contemplates that enhanced capabilities will be attained by enabling a choice between error detection technologies used.

Abstract: Bipolar transistor memory cell and method for use in a random access memory. A pair of state elements are cross coupled so that they assume opposite states in accordance with signals applied thereto, a pair of bipolar pass transistors are connected to respective ones of the state elements for applying signals to the state elements, and current flow through the pass transistors is monitored to determine the states of the state elements.

Abstract: According to the invention, a chipset is provided which powers up in a default state with cacheing disabled and which writes permanently non-cacheable tags into tag RAM entries corresponding to memory addresses being read while cacheing is disabled. Even though no "valid" bit is cleared, erroneous cache hits after cacheing is enabled are automatically prevented since any address which does match a tag in the tag RAM, is a non-cacheable address and will force retrieval directly from main memory anyway. Two cache tag test modes are also described, as is a cache sizing algorithm.

Abstract: A method for cleaning data elements in a memory system accessible by a bus master. A first data element is transferred between the bus master and a fast memory while writing the first element to a dirty element register within the memory system. The first element is then cleaned by writing it from the register to a slow memory within the system without delaying memory access requests for the fast memory.

Abstract: A circuit and method of operation for controlling block-write operations to interleaved memories is disclosed which includes first and second interleave banks of memories, each memory addressable in a normal mode in a block-write mode. Each memory has a plurality of input nodes for receiving data in a normal mode, ones of the input nodes operable to receive data in the block-write mode and other ones of said input nodes not used in the block-write mode. Coupling circuitry couples leads from an output bus to input nodes of the first bank memories which are operable to receive data in the block-write mode and to input nodes in the second bank of memories which are not used in the block-write mode.

Abstract: A data transfer controller for controlling DMA data transfer between a memory area and a peripheral unit. The data transfer controller has a first register which stores address information relative to a predetermined address of the memory area. A DMA control unit uses the first register and a second register to perform the DMA data transfer between the memory area and the peripheral unit. The data transfer controller also has a third register for storing data used for accessing the memory area of the DMA transfer. An updater is used to update the contents of the third register whenever a memory access uses the third register and is different from a memory access associated with data transfer between the memory area and the peripheral unit. Finally, a counter changes the contents of the third register in one direction whenever the data transfer between the memory area and the peripheral unit is performed.

Abstract: A complete digital data storage magnetic tape system for utilization with a host unit comprising a host device, an interface for interfacing the host unit with the DDS system, a controller for encoding and decoding data to and from the magnetic tape, an automatic track follower for performing automatic track following on the magnetic tape, a driver for driving the magnetic tape, a read/write channel for channeling data thereto and therefrom, a read/write head drum for transferring data to and from the magnetic tape, the controller, the automatic track follower, the driver, the read/write channel, and the read/write head drum all being under software programmable control.

Abstract: An information processor for prefetching memory operands stored in an external storage device comprises a first storage for storing addresses used for accessing the external storage device; a selector for selecting either an address in the first storage or data read out of the external storage device; a second storage for storing the contents selected by the selector as well as data to be written in the external storage device; a third storage for storing an address read out of the first or second storage; and a controller. When an error occurs in reading data from the external storage device, the controller controls the selector to select the address in the first storage as an error address. The error address is once stored in the second storage and then transferred to and stored in the third storage.

Abstract: A cell architecture for use in a linear array wafer scale integration includes a plurality of multiplexers, each associated with a boundary of the cell, and each selectively operable to permit ingress to and egress from function logic of the cell by neighboring cells. Each multiplexer is configured to receive and select between input and output busses from and to a neighbor cell adjacent the associated boundary. The output of each multiplexer connects to the output bus of the boundary adjacent to that with which the multiplexer is associated. When such cell architecture is used in wafer scale integration, oriented so that opposing sides of each cell are rotated 180 degrees relative to any cell at any boundary, the multiplexers can be configured to form a linear array of cells that ensures a fixed, known, delay from function logic to function logic of the cells.

Abstract: A cache memory structure comprises a cache memory that has a plurality of ports for reading data from the cache memory and a plurality of ports for writing data into the cache memory. A switching network matrix having controllable switch elements for connecting of the cache memory ports to bus terminals is arranged between the bus terminals and processors, to an instruction unit of a processor, to a main memory, and to the cache memory. The switch elements of the switching network matrix are controlled by a cache memory controller such that the bus terminals can be selectively connected to the write or read ports of the cache memory. With the assistance of the switching network matrix, it becomes possible to select the number of ports of the cache memory to be less than the plurality of bus terminals that access the cache memory.

Abstract: In accordance with the present invention, a memory system capable of indefinite sequential access to a contiguous address space without stutter is provided. The memory system has a memory array divided into left and right halves, column and row decoders, memory output register banks A and B, and control logic. Upon initial access, the control logic determines whether, in the initial access data to be loaded in register banks A and B cross a row address boundary. If a row address boundary is crossed, data loaded into register bank A corresponds to data in one row in the right half of the memory array, and data in register bank B corresponds to data in the left half of the memory array in the next higher row. Thereafter, register banks A and B are interleaved for loading and output of memory data.

Abstract: A hierarchical cache memory includes a high-speed primary cache memory and a lower speed secondary cache memory of greater storage capacity than the primary cache memory. To manage a huge number of data lines interconnecting the primary and secondary cache memories, the hierarchical cache memory is integrated on a plurality of integrated circuits which include all of the interconnecting data lines. Each integrated circuit includes a primary memory and a secondary memory for storing and retrieving data transferred over a first data input line and a first data output line that link the primary memory to a central processing unit. At any given time, a multi-bit word is addressed in the secondary memory, and a corresponding multi-bit word is addressed in the primary memory.

Abstract: A method for performing buffer copy operations in a personal computer system utilizing paged memory mode architecture and having a cache memory. The contents of a first buffer are read into a microprocessor register and simultaneously written into a cache memory. The first buffer is then read again and written to a second buffer, with the actual data values being obtained from the cache memory. This method avoids excessive wait states associated with changing memory pages from the first buffer memory address to the second buffer memory address for each data value.