Abstract: A semiconductor memory device having normal columns and redundant columns includes normal column decoders for designating the normal columns and redundant column decoders for designating the redundant columns so that the bits from the normal columns are combined with the bits from the redundant columns so as to provide an entire byte. The normal column decoders are to be operated simultaneously with the redundant column decoders.

Abstract: A semiconductor a semiconductor memory device including a plurality of normal blocks containing only normal memory cells without a redundant memory cell and a redundant block containing only redundant memory cells.

Abstract: An apparatus and method for controlling memory requests in an information processor is capable of generating an effective address for a first operand and a second operand, both of which are part of an instruction used to transfer data from a first memory location to a second memory location. The first operand indicates the first memory location and the second operand indicates the second memory location. By changing, in response to address overlap of the first and second operands, control of requests for memory accessing by changing the read address of a control memory, useless memory accessing is avoided resulting in faster processing.

Abstract: A Direct Memory Access (DMA) controller (1) of a 2-bus cycle transfer type executes a read cycle first to fetch data from a data source then internally rearranges or aligns the fetched data in accordance with a bus width and/or a storing address of a data destination unit and thereafter executes a write cycle to write the rearranged data in the data destination unit. The DMA controller includes a data register (106) having first and second fields (106-1 and 106-2). Data from the data source is temporarily stored in one of the first and second fields of the data register during the read cycle, and data in the other of the first and second fields is written to the data destination unit during the write cycle.

Abstract: A mass storage subsystem is connectable to a host computer via a host adapter and includes a subsystem bus extending from the host adapter to at least one base unit and a removable disk drive cartridge for use with the base unit. A control signal path extends between the base unit and the removable disk drive cartridge when it is installed and connected within the base unit. The disk drive cartridge includes a housing, at least one storage disk rotatably mounted within the housing, at least one data transducer head within the housing and positionable by a head positioner at selected concentric data storage tracks defined on a storage surface of the storage disk. A bus interface circuit is provided for directly connecting to the subsystem bus when the cartridge is installed and connected within the base unit, and a cartridge controller is provided for controlling operations of the bus interface circuit and the head positioner and for communicating with the base unit via the control signal path.

Abstract: A system includes a main memory having a plurality of sections which each include a plurality of selectively addressable storage locations, a cache memory, and an accessing arrangement for successively requesting data from respective locations in the main memory. A method and apparatus for controlling the system involve assigning each section of the main memory a changeable status condition which is one of a caching enabled status and a caching disabled status, and inhibiting reading and storing of data by the cache memory when data requested by the accessing unit is in one of the sections of the main memory having the caching disabled status. An alternative method and apparatus for controlling the system involve selective operation in a mode in which data in the cache memory is updated even when reading of data from the cache memory is inhibited.

Abstract: There is disclosed a semiconductor memory device as a multi-port DRAM having split SAM registers. This memory device comprises a RAM section of which memory area is halved into first and second cell arrays by the value of a specific bit constituting a portion of a column address, a SAM section comprised of first and second registers, first and second data transfer paths for carrying out data transfer from the first and second cell arrays to the first and second registers, respectively, third and fourth data transfer paths for shifting data from the first and second cell arrays to the second and first data transfer paths, respectively, and first, second third and fourth transfer controllers are inserted into the first, second third and fourth data transfer paths, respectively. Thus, with this multi-port DRAM, the degree of freedom of mapping is improved in a frame buffer.

Abstract: An improved NAND type EEPROM is disclosed, in which one selecting transistor and a plurality of memory transistors constituting one memory block are connected in series, a tunnel region for writing/erasing signal charges is isolated from a read transistor region for reading presence/absence of stored charge in each of the memory transistors. The plurality of memory transistors share one selecting transistor and the read transistor region and the selecting transistor region are isolated from each other, so that the memory block can be made small and the threshold values of the plurality of memory transistors are not influenced by the number of the memory transistors.

Abstract: A computer system operable as a virtual machine system capable of accessing multiple virtual address spaces, which has an access register translation means for translating a space identifier into an origin address of a table for address translation and a translation pair memory for storing translation pairs of the space identifiers and the associated origin addresses. In each entry of the translation pair memory, a field is provided in association with the translation pair, for storing a machine identifier of the guest virtual machine associated with the translation pair. When accessing a virtual address space, a guest virtual machine makes reference only to the associated translation pair based on the virtual machine identifier thereof.

Abstract: A method and apparatus for programming a mass storage device of the type having a plurality of memory word locations. The memory word locations are organized into a plurality of addressable columns and addressable rows, each memory word location capable of storing one byte word in response to at least two programming steps. Each programming step for a selected memory word location requires a predetermined time period before a subsequent programming step can be processed by the selected memory word location. A first programming step is applied to a first memory word location. The first programming step is applied sequentially to other memory word locations while the first programming step is being processed by the first memory word location. A second programming step is applied to the first memory word location while the first programming step is being process by the other memory word locations.

Abstract: An integrated circuit, for use as a cache subsystem, implements a cache static random access memory (SRAM) storage array, a central processor unit (CPU) bus interface and a main memory bus interface. The CPU bus and main memory bus interfaces include multiplexers, buffers, and local control for optimizing burst read and write operations to and from the CPU bus. These circuits allow a full cache line to be read or written in a single access of the SRAM array. Control logic is utilized within the CPU bus interface for controlling CPU bursts in the order defined by the CPU. The memory bus interface includes internal buffers used in performing memory bus reads, write-throughs, write-backs and snoops. Tracking logic is employed for determining the appropriate internal buffer to be utilized for a particular memory bus cycle. Additionally, a data path is included for transparently passing data between the CPU and memory bus interfaces without disturbance of the SRAM array.

Abstract: A system and method for optimizing the utilization of a cache memory in an input/output controller in a computer system which also includes a central processing unit and a plurality of direct access storage devices. The optimizing system calculates a demotion time where the demotion time is an approximation of the length of time that a track of data will reside in the cache memory in the input/output controller after its last input/output request from the central processing unit. The optimizing system further intercepts an input/output request from the central processing unit for a requested track of data, determines an elapsed time between successive input/output requests from the central processing unit for the requested track of data, determines whether the elapsed time is greater than the demotion time and optimizes the requested track of data by inhibiting the requested track of data from being loaded into the cache memory if the elapsed time is greater than the demotion time.

Abstract: A semiconductor memory device operable for reading and writing in a normal mode and in a test mode is divided into memory cell sections each having blocks of memory cells. Data bus lines are connected to the respective blocks, and switches interconnect data bus lines connected to blocks of the different sections. The switch are made conductive during reading and writing in the normal mode and during writing in the test mode, and nonconductive during reading in the test mode. Input data are applied onto the data bus lines connected one of the blocks for writing in the blocks of the sections simultaneously during writing in the normal mode and in the test mode. In the normal mode, data are read out of the blocks of the sections through the data bus lines connected to the above-mentioned one of the blocks. In the test mode, the data are read out of the blocks of the sections through the data bus lines connected to the respective blocks.

Abstract: A local processor is connected to one port of a dual port memory controller. A bus having a BURST signal line is connected to the other port. The memory controller controls access to a local memory. A remote processor can perform a semaphore operation on a semaphore stored in the local memory by translating a LOCK signal from the remote processor into a bus BURST signal that is activated for a period allowing the remote processor to read and modify the semaphore. While the semaphore operation is being performed, the local processor can access the local memory.

Abstract: A system for transferring interleaved data objects in mass storage devices into separate destinations in a system memory is described. The method includes the steps of determining for each of the data objects a destination address and a size; one time seeking of a data object from a location of the mass storage means; transferring data from the data object into the destination address, wherein the data has a size equal to the size for the data object; and repeating the transferring step for subsequent data objects.

Abstract: A method and apparatus for use in read/write operations by a processor that reads and writes information in first and second address formats. The method and apparatus include a memory and a memory mapper for remapping according to a predetermined scheme those memory fragments not containing information stored in the first address format. Memory fragments are thus accessible to the processor for reading and writing information in the second address format. Such remapping operation results in the memory fragments appearing logically contiguous. In the preferred embodiment, the first address format is an x-y address format and the second address format is a linearly addressable format. An alternative embodiment discloses the use of a second memory for reading and writing information in the second address format. In that embodiment, the memory mapper remaps the memory fragments to appear logically contiguous with said second memory.

Abstract: A method and process for providing a memory dump of less than the entire contents of memory is provided. The memory locations to be dumped are selected on the basis of recency of use, so that there is a high probability that portions of memory needed for analysis or evaluation of the computer system will be included in the selective dump. Preferably, the select ion is made on the basis of information or hardware which is already provided in the computer system. In one preferred embodiment, memory to be dumped is selected on the basis of memory locations encoded for by a translation lookaside buffer.

Abstract: The invention comprises methods and apparatuses for interleaving a number of memory cards of different sizes. A restricted range modulo-N adder for identifying and selecting the correct interleave card is provided. Another aspect of the invention provides a computer system with flexible memory interleaving capability.

Abstract: A semiconductor memory device comprises a memory cell for storing a binary data, a first reference cell storing a first logic level of a binary data, a second reference cell storing a second logic level of a binary data, a first load circuit connected to the memory cell, a second load circuit connected to the first reference cell, a third load circuit connected to the second reference cell, and a data detection circuit for detecting the stored data of the memory cell by comparing an output from the first load circuit with the outputs from the second and third load circuits.

Abstract: A mechanism for exchanging information between SCSI devices which allows for specifying multiple source or destination buffers. The mechanism includes a first apparatus for generating at least one move instruction which when executed by the SCSI manager either writes or reads the specified number of bytes to or from that buffer address and subsequently adds the offset field value to the buffer address to create a current buffer address. The current buffer address and the buffer address may be non-contiguous. The mechanism also has a second apparatus for generating at least one looping instruction by which the SCSI manager branches the offset number of instructions until the number is exhausted. This allows the SCSI manager to repeat instructions. During each repetition of the move instruction, the buffer address location gets incremented by the value in the offset field.