Abstract: A method for forming a chip package structure is provided. The method includes forming a conductive structure over a substrate. The substrate includes a dielectric layer and a wiring layer in the dielectric layer, and the conductive structure is electrically connected to the wiring layer. The method includes forming a first molding layer over the substrate and surrounding the conductive structure. The method includes forming a redistribution structure over the first molding layer and the conductive structure. The method includes bonding a chip structure to the redistribution structure.

Abstract: The present disclosure provides a display panel, a manufacturing method thereof, and a display device. The display panel includes an array substrate which includes a plurality of pixel regions defined by a plurality of gate lines intersected with a plurality of data lines. Each of the pixel regions includes an aperture region, a non-aperture region surrounding the aperture region, and a spacer disposed in the non-aperture region. Each of the pixel regions includes a padding structure provided in the non-aperture region. The padding structure includes a first pad and a second pad located in the non-aperture region. The first pad and the second pad are located at two sides of the spacer, respectively. The first pad and the second pad are located at two sides of the gate line, respectively. The padding structure is configured to prevent the spacer from moving into the aperture region.

Abstract: An array substrate having a display region and a non-display region, includes signal lines at least located in the display region, signal line leads located in the non-display region, connection portions located in the non-display region for coupling the signal lines to the signal line leads, and the signal lines and the signal line leads are two separate portions.

Abstract: A semiconductor device includes a substrate, a channel layer, an insulating layer, source/drain contacts, a gate dielectric layer, and a gate electrode. The channel layer over the substrate and includes two dimensional (2D) material. The insulating layer is on the channel layer. The source/drain contacts are over the channel layer. The gate dielectric layer is over the insulating layer and the channel layer. The gate electrode is over the gate dielectric layer and between the source/drain contacts.

Abstract: Provided is a semiconductor package. The semiconductor package may include a substrate, a semiconductor chip on the substrate, a passive element on the substrate, a conductive structure on the substrate, and an interposer substrate on the semiconductor chip, the passive element, and the conductive structure. The interposer substrate may be electrically connected to the conductive structure. A height of the passive element may be greater than a height of the semiconductor chip.

Abstract: Devices and methods for a vertical field effect transistor (VTFET) semiconductor device include recessing a gate dielectric and a gate conductor of a vertical gate structure below a top of a vertical fin to form openings between the top of the vertical fin and an etch stop layer, the top of the vertical fin being opposite to a substrate at a bottom of the vertical fin. A spacer material is deposited in the openings to form a spacer corresponding to each of the openings. Each spacer is recessed below the top of the vertical fin. A top spacer is selectively deposited in each of the openings to line the etch stop layer and the spacer such that the top of the vertical fin is exposed above the top spacer and the spacer is covered by the top spacer. A source/drain region is formed on the top of the vertical fin.

Abstract: A flux-biasing device includes a set of magnetic flux generating members. A first magnetic flux generating member is configured to magnetically interact with a first qubit from a set of qubits of a quantum processor such that a first magnetic flux of the first member causes a first change in a first resonance frequency of the first qubit by a first frequency shift value. Each non-corresponding magnetic flux generating member of the set is well separated from qubits corresponding to other magnetic flux generating members of the set such that qubits corresponding to other members exhibit less than a threshold value of resonance frequency shift as a result of a magnetic flux of a non-corresponding member.

Abstract: A method for manufacturing a display device is provided. The method includes providing an array module having at least one first alignment mark. The method also includes providing a light-emitting module having at least one second alignment mark. The method further includes aligning the light-emitting module and the array module by the at least one first alignment mark and the at least one second alignment mark. In addition, the method includes bonding the light-emitting module onto the array module.

Abstract: A semiconductor device and a manufacturing method of the same are provided. The method includes forming a plurality of first conductive structures and a first dielectric layer between the first conductive structures on a substrate. The method also includes forming a trench between the first dielectric layer and the first conductive structures. The method further includes forming a liner material on a sidewall and a bottom of the trench. In addition, the method includes forming a conductive plug on the liner material in the trench. The method also includes removing the liner material to form an air gap, and the air gap is located between the conductive plug and the first dielectric layer.

Abstract: A multi-level cell thin-film transistor memory and a method of fabricating the same, a structure of which memory comprises sequentially from down to top: a gate electrode, a charge blocking layer, a charge trapping layer, a charge tunneling layer, an active region, and source and drain electrodes; wherein the charge tunneling layer fully encloses the charge trapping layer so as to completely isolate the charge trapping layer from the ambience, which prevents change of physical properties and chemical compositions of the charge trapping layer during the annealing treatment, reduces loss of charges stored in the charge trapping layer, and enhances data retention property and device performance stability; a metal oxide semiconductor thin film is utilized as the charge trapping layer of the memory, which implements multi-level cell storage and improves storage density.

Abstract: Provided is a pressure-strain sensor including a graphene structure having a three-dimensional porous structure, planar sheets provided on a surface of the graphene structure, and a polymer layer configured to cover the graphene structure and the planar sheets, wherein each of the planar sheets contains a transition metal chalcogenide compound.

Abstract: A semiconductor device includes a substrate including traces, wherein the traces protrude above a top surface of the substrate; a prefill material over the substrate and between the traces, wherein the prefill material directly contacts peripheral surfaces of the traces; a die attached over the substrate; and a wafer-level underfill between the prefill material and the die.

Abstract: A stacked FinFET mask-programmable read only memory (ROM) is provided. The stacked FinFET mask-programmable ROM includes a fin structure extending upward from an insulator layer. In accordance with the present application, the fin structure includes, from bottom to top, a lower programmable semiconductor fin portion having a first threshold voltage, an insulator fin portion, and an upper programmable semiconductor fin portion having a second threshold voltage. A lower gate structure contacts a sidewall of the lower programmable semiconductor fin portion, and an upper gate structure contacts a sidewall of the upper programmable semiconductor fin portion.

Abstract: A light-emitting element and a light-emitting device having low light loss, high luminance, and high light extraction efficiency are provided. The light-emitting element includes: a semiconductor structure layer having a light-emitting layer; a light-transmitting substrate provided on the semiconductor structure layer; a wavelength conversion layer disposed on the light-transmitting substrate; a light-transmitting covering member configured to cover at least a part of a side surface of the light-transmitting substrate and have transparency to light from the light-emitting layer; and a light-shielding member configured to entirely cover surfaces including a surface of the light-transmitting covering member, and including a side surface of the semiconductor structure layer, a side surface of the light-transmitting substrate, and a side surface of the wavelength conversion layer.

Abstract: Semiconductor devices and methods of forming the same are provided. Semiconductor devices may include first and second active patterns on a substrate. Each of the first and second active patterns may extend in a first direction. The first and second active patterns may be aligned along the first direction and may be separated by a first trench extending in a second direction. The first trench may define a first sidewall of the first active pattern. The semiconductor devices may also include a channel pattern including first and second semiconductor patterns stacked on the first active pattern, a dummy gate electrode on the channel pattern and extending in the second direction, and a gate spacer on one side of the dummy gate electrode, the one side of the dummy gate electrode being adjacent to the first trench. The gate spacer may cover a first sidewall of the first active pattern.

Abstract: A display panel and a method for manufacturing same are provided. The display panel includes a flexible film layer, a thin film transistor switching device, an insulation layer, a planarization layer, an organic light-emitting diode display device, and a package layer. A part of the planarization layer fills a first through-hole of the insulation layer. A first metal component and a second metal component of the display panel are disposed on two sides of the first through-hole, and a third metal component of the display panel is connected to the first metal component and the second metal component, so as to improve a bending capability of the display panel.

Abstract: Monolithic LED chips are disclosed comprising a plurality of active regions on a submount, wherein the submount comprises integral electrically conductive interconnect elements in electrical contact with the active regions and electrically connecting at least some of the active regions in series. The submount also comprises an integral insulator element electrically insulating at least some of the interconnect elements and active regions from other elements of the submount. The active regions are mounted in close proximity to one another to minimize the visibility of the space during operation. The LED chips can also comprise layers structures and compositions that allow improved reliability under high current operation.

Abstract: Multiple component package structures are described in which an interposer chiplet is integrated to provide fine routing between components. In an embodiment, the interposer chiplet and a plurality of conductive vias are encapsulated in an encapsulation layer. A first plurality of terminals of the first and second components may be in electrical connection with the plurality of conductive pillars and a second plurality of terminals of first and second components may be in electrical connection with the interposer chiplet.

Abstract: A method includes bonding a first package to a second package to form a third package. The first package is an Integrated Fan-Out (InFO) package including a plurality of package components, and an encapsulating material encapsulating the plurality of package components therein. The plurality of package components include device dies. The method further includes placing at least a portion of the third package into a recess in a Printed Circuit Board (PCB). The recess extends from a top surface of the PCB to an intermediate level between the top surface and a bottom surface of the PCB. Wire bonding is performed to electrically connect the third package to the PCB.

Abstract: Embodiments of the invention are directed to an integrated optogenetic device. The integrated optogenetic includes a substrate layer having a first substrate region and a second substrate region. The device further includes a first contact formed over the substrate layer in the first substrate region and a second contact layer formed over the substrate layer in the second region. In addition, the device includes a light-emitting diode (LED) structure communicatively coupled to the first contact layer and a biosensor element communicatively coupled to the second contact layer. The first contact layer is configured to operate as a bottom contact that provides electrical contact to the LED structure. The first contact layer is further configured to be substantially lattice matched with the substrate layer and a bottom layer of the LED structure.