Patents Examined by Joseph M Galvin, III
  • Patent number: 10903377
    Abstract: Method and structural embodiments are described which provide an integrated structure using polysilicon material having different optical properties in different regions of the structure.
    Type: Grant
    Filed: April 15, 2019
    Date of Patent: January 26, 2021
    Assignees: Micron Technology, Inc., Massachusetts Institute of Technology
    Inventors: Roy Meade, Karan Mehta, Efraim Megged, Jason Orcutt, Milos Popovic, Rajeev Ram, Jeffrey Shainline, Zvi Sternberg, Vladimir Stojanovic, Ofer Tehar-Zahav
  • Patent number: 10889490
    Abstract: An electrothermally actuated microelectromechanical and/or nanoelectromechanical structure including a stationary portion, at least one portion which is movable relative to the stationary portion, at least one electrothermal actuation beam which makes it possible to cause an electric current to flow from the stationary portion to the movable portion, is mechanically connected to the movable portion and is intended to move the movable portion relative to the stationary portion by electrothermal actuation, and at least one electrically conductive connection element electrically connecting the movable portion to the stationary portion, the actuation beam having a thickness of no greater than half one thickness of the movable portion and no greater than half one thickness of the connection element.
    Type: Grant
    Filed: October 20, 2016
    Date of Patent: January 12, 2021
    Assignees: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, SAFRAN ELECTRONICS & DEFENSE
    Inventors: Guillaume Jourdan, Guillaume Lehee
  • Patent number: 10886391
    Abstract: Transistors and methods of forming the same include forming a fin that has an active layer between two sacrificial layers. Material is etched away from the two sacrificial layers in a region of the fin. A gate stack is formed around the active layer in the region. The active layer is etched after forming the gate stack to form a quantum dot.
    Type: Grant
    Filed: June 5, 2019
    Date of Patent: January 5, 2021
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Xin Miao, Wenyu Xu, Chen Zhang
  • Patent number: 10886371
    Abstract: A silicon carbide semiconductor device, including a semiconductor substrate having first and second epitaxial layers. The second epitaxial layer is formed on a first main surface of the semiconductor substrate, and includes first and second semiconductor regions, selectively provided in a surface layer of the second epitaxial layer respectively in the active region and the border region, and a third semiconductor region. The semiconductor device further includes a trench penetrating the first and third semiconductor regions to reach the first epitaxial layer, a gate electrode provided in the trench via a gate insulating film, a first electrode electrically connected to the first and third semiconductor regions, and a second electrode provided at a second main surface of the semiconductor substrate. The second semiconductor region is separate from the first semiconductor region.
    Type: Grant
    Filed: April 19, 2019
    Date of Patent: January 5, 2021
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Takashi Tsuji, Akimasa Kinoshita
  • Patent number: 10886293
    Abstract: A method of fabricating a semiconductor device includes: forming alternately a plurality of first films and a plurality of second films on a substrate, forming a hole in the first and second films, forming a first metal layer on a surface of the hole, and removing the first metal layer from a bottom of the hole. The method further includes forming a second metal layer on a surface of the first metal layer after removing the first metal layer from the bottom of the hole. The method further includes processing the bottom of the hole exposed from the first and second metal layers to increase a depth of the hole.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: January 5, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Kenichi Yoshikawa
  • Patent number: 10879350
    Abstract: A method for forming a transistor device includes: implanting dopant atoms of a first doping type and dopant atoms of a second doping type into opposite sidewalls of each of a plurality of trenches of a first semiconductor layer having a basic doping of the first doping type, the dopant atoms of the first doping type having a smaller diffusion coefficient than the dopant atoms of the second doping type; filling each trench with a second semiconductor layer of the first doping type; and diffusing the dopant atoms of the first doping type and the dopant atoms of the second doping type such that a plurality of first regions of the first doping type and a plurality of second regions of the second doping type are formed. The second regions are spaced apart from each other. Each first region is at least partially arranged within a respective second region.
    Type: Grant
    Filed: March 15, 2019
    Date of Patent: December 29, 2020
    Assignee: Infineon Technologies Austria AG
    Inventor: Hans Weber
  • Patent number: 10879279
    Abstract: Provided is a method of manufacturing a display, a display, and a liquid crystal television that can improve productivity and make a grain size uniform. A method of manufacturing a display includes: (A) deriving, when a laser beam is applied to an aSi film 18 provided on a substrate 11 to thereby polycrystallize the aSi film 18 and form a pSi film 14, a relationship between energy density of the laser beam and a grain size of the pSi film 14; (B) selecting a predetermined range of the energy density in the derived relationship; and (C) irradiating a first area including the aSi film 18 with a laser beam at energy density in the selected range of the energy density to thereby polycrystallize the aSi film 18 and form the pSi film 14.
    Type: Grant
    Filed: April 16, 2018
    Date of Patent: December 29, 2020
    Assignee: THE JAPAN STEEL WORKS, LTD.
    Inventor: Naoyuki Kobayashi
  • Patent number: 10861869
    Abstract: An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. Memory stack structures are formed through the alternating stack. Each of the memory stack structures includes respective charge storage elements and a respective vertical semiconductor channel contacting an inner sidewall of the respective charge storage elements. The sacrificial material layers are replaced with electrically conductive layers. A polycrystalline aluminum oxide blocking dielectric layer is provided between each charge storage element and a neighboring one of the electrically conductive layers. The polycrystalline aluminum oxide blocking dielectric layer is formed by: depositing an amorphous aluminum oxide layer, converting the amorphous aluminum oxide layer into an in-process polycrystalline aluminum oxide blocking dielectric layer, and by thinning the in-process polycrystalline aluminum oxide blocking dielectric layer.
    Type: Grant
    Filed: January 8, 2019
    Date of Patent: December 8, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Ryo Nakamura, Yu Ueda, Tatsuya Hinoue, Shigehisa Inoue, Genta Mizuno, Masanori Tsutsumi
  • Patent number: 10854784
    Abstract: A method for producing an electrical contact on a semiconductor layer and a semiconductor component having an electrical contact are disclosed. In an embodiment a method includes providing a semiconductor layer, forming a plurality of contact rods on the semiconductor layer, wherein the contact rods are formed by a first material and a second material, wherein the first material is applied to the semiconductor layer and the second material is applied to the first material, and wherein a lateral structure of the first material is self-organized, forming a filling layer on the contact rods and in intermediate spaces between the contact rods and exposing the contact rods.
    Type: Grant
    Filed: September 26, 2017
    Date of Patent: December 1, 2020
    Assignee: OSRAM OLED GMBH
    Inventors: Martin Rudolf Behringer, Brendan Holland, Jana Sommerfeld, Sabine vom Dorp
  • Patent number: 10854510
    Abstract: Aspects of the present invention relate to approaches for forming a narrow source-drain contact in a semiconductor device. A contact trench can be etched to a source-drain region of the semiconductor device. A titanium liner can be deposited in this contact trench such that it covers substantially an entirety of the bottom and walls of the contact trench. An x-metal layer can be deposited over the titanium liner on the bottom of the contact trench. A titanium nitride liner can then be formed on the walls of the contact trench. The x-metal layer prevents the nitriding of the titanium liner on the bottom of the contact trench during the formation of the nitride liner.
    Type: Grant
    Filed: August 26, 2017
    Date of Patent: December 1, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Min Gyu Sung, Kwanyong Lim, Hiroaki Niimi
  • Patent number: 10847606
    Abstract: A system-on-chip (SOC) device comprises a first capacitor in a first region, a second capacitor in a second region, and may further comprise a third capacitor in a third region, and any additional number of capacitors in additional regions. The capacitors may be of different shapes and sizes. A region may comprise more than one capacitor. Each capacitor in a region has a top electrode, a bottom electrode, and a capacitor insulator. The top electrodes of all the capacitors are formed in a common process, while the bottom electrodes of all the capacitors are formed in a common process. The capacitor insulator may have different number of sub-layers, formed with different materials or different thickness. The capacitors may be formed in an inter-layer dielectric layer or in an inter-metal dielectric layer. The regions may be a mixed signal region, an analog region, a radio frequency region, a dynamic random access memory region, and so forth.
    Type: Grant
    Filed: November 27, 2018
    Date of Patent: November 24, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Chi Tu, Wen-Chuan Chiang, Chen-Jong Wang
  • Patent number: 10832945
    Abstract: Techniques to improve CD width and depth uniformity between features with different layout densities are provided. In one aspect, a method of forming a contact structure includes: patterning features in different regions of a dielectric at different layout densities whereby, due to etch loading effects, the features are patterned to different depths in the dielectric and have different bottom dimensions; depositing a sacrificial spacer into/lining the features whereby some of the features are pinched-off by the sacrificial spacer; opening up the sacrificial spacer at bottoms of one or more of the features that are not pinched-off by the sacrificial spacer; selectively extending the one or more features in the dielectric, such that the one or more features have a discontinuous taper with a stepped sidewall profile; removing the sacrificial spacer; and filling the features with a conductive material to form the contact structure. A contact structure is also provided.
    Type: Grant
    Filed: February 15, 2019
    Date of Patent: November 10, 2020
    Assignee: International Business Machines Corporation
    Inventors: Nicole Saulnier, Indira Seshadri, Lawrence A. Clevenger, Leigh Anne H. Clevenger, Gauri Karve, Fee Li Lie, Isabel Cristina Chu, Hosadurga Shobha, Ekmini A. De Silva
  • Patent number: 10811412
    Abstract: A FinFET including a gate stack, a semiconductor fin embedded in the gate stack, a source and a drain disposed is provided. The semiconductor fin extends along a widthwise direction of the gate stack and has a first concave and a second concave exposed at sidewalls of the gate stack respectively. The source and drain are disposed at two opposite sides of the gate stack. The source includes a first portion in contact with and embedded in the first concave. The drain includes a second portion in contact with and embedded in the second concave. The first portion and the second portion are covered by the gate stack.
    Type: Grant
    Filed: July 28, 2019
    Date of Patent: October 20, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Che-Cheng Chang, Chih-Han Lin, Horng-Huei Tseng
  • Patent number: 10804438
    Abstract: A semiconductor light-emitting device includes a semiconductor layer, having a major surface and generating light, a light transmitting layer, having alight transmitting property and covering the major surface of the semiconductor layer, a light reflecting layer, having a light reflecting property and covering the light transmitting layer, and a bonding material diffusion region, formed in a surface layer portion of the light reflecting layer in a boundary portion between the light transmitting layer and the light reflecting layer and having an element having a property of being high in adhesion force with respect to the light transmitting layer more so than an element constituting the light reflecting layer.
    Type: Grant
    Filed: October 15, 2018
    Date of Patent: October 13, 2020
    Assignee: ROHM CO., LTD.
    Inventor: Yohei Ito
  • Patent number: 10804499
    Abstract: [Object] To provide a light emitting element that enables efficient light extraction and offers low power consumption. [Solution] A light emitting element including: a lower electrode disposed on a support layer; first members disposed on the support layer so as to surround the lower electrode to form a recess structure, the first members each having a void inside; an organic layer disposed on the lower electrode and the first members and along the recess structure, the organic layer containing an organic luminescent material; an upper electrode disposed on the organic layer and along the recess structure; and a second member disposed above the upper electrode such that the recess structure is embedded in the second member, the second member having a higher refractive index than the first members.
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: October 13, 2020
    Assignee: Sony Semiconductor Solutions Corporation
    Inventor: Kimihiro Shinya
  • Patent number: 10804398
    Abstract: A device including source-drain epitaxy contacts with a trench silicide (TS) liner wrapped around the source-drain contacts, and method of production thereof. Embodiments include a device having a gate structure formed over a substrate; source-drain epitaxy contacts including a trench silicide (TS) liner covering the source-drain epitaxy contacts; TS contacts formed on the TS liner over the source-drain epitaxy contacts; and a dielectric pillar disposed in a TS cut between the source-drain epitaxy contacts. The TS liner wraps around the source-drain epitaxy contacts, including bottom negatively tapered surfaces of the source-drain epitaxy contacts.
    Type: Grant
    Filed: October 15, 2018
    Date of Patent: October 13, 2020
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Julien Frougier, Ruilong Xie
  • Patent number: 10804282
    Abstract: An alternating stack of insulating layers and sacrificial material layers is formed over a substrate, and memory stack structures are formed through the alternating stack. A backside trench is formed through the alternating stack, and backside recesses are formed by removing the sacrificial material layers. An undoped aluminum oxide backside blocking dielectric layer is formed in the backside recesses and on sidewalls the backside trench. A portion of the undoped aluminum oxide backside blocking dielectric layer located at an upper end of the backside trench is converted into a carbon-doped aluminum oxide layer. An electrically conductive material is deposited in the backside recesses and at peripheral regions of the backside trench. The electrically conductive material at the peripheral regions of the backside trench is removed by an etch process, with the carbon-doped aluminum oxide layer providing etch resistivity during the etch process.
    Type: Grant
    Filed: February 11, 2019
    Date of Patent: October 13, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Ashish Baraskar, Fei Zhou, Ching-Huang Lu, Raghuveer S. Makala
  • Patent number: 10790459
    Abstract: A stretchable film includes a first region including a plurality of first patterns having a concave polygonal shape. The stretchable film also includes a second region including a plurality of second patterns having a concave polygonal shape. The stretchable film further includes a buffer region between the first region and the second region.
    Type: Grant
    Filed: January 11, 2019
    Date of Patent: September 29, 2020
    Assignee: Samsung Display Co., Ltd.
    Inventors: Hye-Jin Joo, Won-Il Choi, Jong-Ho Hong
  • Patent number: 10777713
    Abstract: A method of producing an optoelectronic lighting device includes forming a volume emitter such that it is at least partly transmissive to generated electromagnetic radiation, forming a concavely formed, optically transparent frame element including a curable, flowable material including phosphor particles at a side region of the volume emitter, wherein forming a conversion layer that converts the electromagnetic radiation into a second wavelength range is carried out by a sedimentation process of phosphor particles, and the conversion layer is formed within an optically transparent frame element in a manner adjoining an optically active region, forming a reflection element on the optically transparent frame element, and forming a conversion element that converts the electromagnetic radiation into a second wavelength range, wherein the conversion element is formed in a manner overlapping at least a second surface of the volume emitter and frame element.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: September 15, 2020
    Assignee: OSRAM OLED GmbH
    Inventor: Ivar Tangring
  • Patent number: 10770688
    Abstract: A display device including a display panel including a display area and a non-display area surrounding the display area; a window disposed above the display panel; a driving circuit chip disposed in the non-display area and mounted on the display panel; and a light-scattering member interposed between the display panel and the window. The light-scattering member overlaps with the driving circuit chip and contains scattering particles.
    Type: Grant
    Filed: December 10, 2018
    Date of Patent: September 8, 2020
    Assignee: Samsung Display Co., Ltd.
    Inventors: Nu Ree Um, Sang Eun Moon, Jin Hee Jang