Abstract: A method is presented for forming equal thickness gate spacers for a CMOS (complementary metal oxide semiconductor) device, the method includes forming a PFET (p-type field effect transistor) device and an NFET (n-type field effect transistor) device each including gate masks formed over dummy gates, forming PFET epi growth regions between the dummy gates of the PFET device, forming NFET epi growth regions between the dummy gates of the NFET device, depositing a nitride liner and an oxide over the PFET and NFET epi growth regions, the nitride liner and oxide extending up to the gate masks, and removing the dummy gates and the gate masks to form HKMGs (high-k metal gates) between the PFET and NFET epi growth regions.

Abstract: A method of fabricating a semiconductor device is described. A plurality of first films and a plurality of second films are alternately formed on a substrate. A hole is formed in the first and second films. A first metal layer is formed on a surface of the hole. The first metal layer is removed from a bottom surface of the hole. A second metal layer may be formed on a surface of the first metal layer after removing the first metal layer from the bottom surface of the hole. The bottom of the hole exposed from the first and second metal layers may be processed to increase a depth of the hole.

Abstract: Monolithic LED chips are disclosed comprising a plurality of active regions on a submount, wherein the submount comprises integral electrically conductive interconnect elements in electrical contact with the active regions and electrically connecting at least some of the active regions in series. The submount also comprises an integral insulator element electrically insulating at least some of the interconnect elements and active regions from other elements of the submount. The active regions are mounted in close proximity to one another to minimize the visibility of the space during operation. The LED chips can also comprise layers structures and compositions that allow improved reliability under high current operation.

Abstract: The present disclosure, in some embodiments, relates to a semiconductor device. The semiconductor device has a gate stack arranged over a first surface of a substrate. A doped isolation feature is arranged within the substrate along opposing sides of the gate stack. A photodetector is also arranged within the substrate. An isolation well region extends below the gate stack and contacts the doped isolation feature along a horizontal plane that is parallel to the first surface and that intersects sides of the photodetector.

Abstract: At least one conductive line in a dielectric layer over a substrate is recessed to form a channel. The channel is self-aligned to the conductive line. The channel can be formed by etching the conductive line to a predetermined depth using a chemistry comprising an inhibitor to provide uniformity of etching independent of a crystallographic orientation. A capping layer to prevent electromigration is deposited on the recessed conductive line in the channel. The channel is configured to contain the capping layer within the width of the conductive line.

Abstract: A method for forming a thermally stable spacer layer is disclosed. The method includes first disposing a substrate in an internal volume of a processing chamber. The substrate has a film formed thereon, the film including silicon, carbon, nitrogen, and hydrogen. Next, high pressure steam is introduced into the processing chamber. The film is exposed to the high pressure steam to convert the film to reacted film, the reacted film including silicon, carbon, oxygen, and hydrogen.

Abstract: Semiconductor memory devices and methods for manufacturing the same are provided. The device may include vertical channel structures that are two-dimensionally arranged on a substrate and vertically extend from the substrate. The device may also include bit lines on the vertical channel structures, and each of the bit lines may be commonly connected to the vertical channel structures arranged in a first direction. The device may further include common source lines that extend between the vertical channel structures in a second direction intersecting the first direction and a source strapping line that is disposed at the same vertical level as the bit lines and electrically connects the common source lines to each other.

Abstract: A flux-biasing device includes a set of magnetic flux generating members. A first magnetic flux generating member is configured to magnetically interact with a first qubit from a set of qubits of a quantum processor such that a first magnetic flux of the first member causes a first change in a first resonance frequency of the first qubit by a first frequency shift value. Each non-corresponding magnetic flux generating member of the set is well separated from qubits corresponding to other magnetic flux generating members of the set such that qubits corresponding to other members exhibit less than a threshold value of resonance frequency shift as a result of a magnetic flux of a non-corresponding member.

Abstract: This semiconductor device includes: an n-type SiC drift layer; a p-type base region; an n-type source region selectively embedded in the top part of the base region; p-type base contact regions selectively embedded in the top part of the base region so as to form a first gap with the source region along the <11-20> direction; a gate electrode provided via a gate insulating film; and an n-type drain region. The top surface of the drain region has an off-angle relative to the <11-20> direction towards the <0001> direction, and an alignment mark for positioning is formed on the top surface. The drift layer and the base region are epitaxially grown films, and a width wg of the first gap is set in accordance with a positional deviation width of the alignment mark caused by the off-angle and epitaxial growth.

Abstract: An organic light-emitting device is disclosed. The organic light-emitting device includes light-emitting layers that emit light of the same color in a stack structure. The phosphorescence and fluorescence characteristics at the exit side and the inside of the organic light-emitting device are adjusted to improve a viewing angle, lifetime, and efficiency.

Abstract: Mold compound transfer systems and methods for making mold compound transfer systems are disclosed herein. A method configured in accordance with a particular embodiment includes providing a sheet mold compound, and dispensing a granular mold compound directly on the sheet mold compound. The sheet mold compound can have a first density and the overall granular mold compound can have a second density less than the first density. The method further comprises transferring the solid sheet carrying the dispensed granular mold compound to a molding machine without using a release film.

Abstract: Various embodiments relate to a semiconductor package structure. The semiconductor package structure includes a first chip having a first surface and a second surface opposite the first surface. The semiconductor package structure further includes a supporter surrounding an edge of the first chip, and the supporter includes a recessed portion. The semiconductor package structure further includes a conductive layer disposed over the first surface of the first chip and electrically connected to the first chip. The semiconductor package structure further includes an insulation layer disposed over the first surface of the first chip. The semiconductor package structure further includes an encapsulant between the first chip and the supporter and surrounding at least the edge of the first chip.

Abstract: A semiconductor structure includes a semiconductor substrate and a conductive feature formed over the semiconductor substrate, an etch stop layer formed over the conductive feature, a dielectric layer formed over the etch stop layer, and a contact formed in a contact trench within the dielectric layer. The bottom of the contact is disposed over a top surface of the conductive feature. The semiconductor structure further includes a self-aligned sealing oxide layer formed on the dielectric layer. The self-aligned sealing oxide layer directly contacts the dielectric layer from a bottom-most portion of the self-aligned sealing oxide layer to a top-most portion of the self-aligned sealing oxide layer.

Abstract: A top surface of a substrate is provided with a detection element for detecting electromagnetic radiation. A refractive element is formed by a portion of a cover element, which is attached to the substrate, so that the refractive element is arranged facing the detection element. The refractive element may be arranged within a recess of the cover element, so that a cavity is formed between the detection element and the refraction element.

Abstract: The present disclosure relates to methods of protecting a structure of an integrated circuit (IC) from rework, and more particularly, to methods of protecting a structure of an IC without impacting the critical dimension or the profile of the structure. For example, a method of protecting a structure of an IC from rework may include forming a first layer on a second layer; forming one or more first openings in the first layer, the first openings exposing a top surface of the second layer; selectively growing a Group VIII metal within the one or more first openings, thereby forming one or more first plugs; forming one or more final openings in the first layer; and removing the one or more first plugs.

Abstract: An approach to provide an electronic assembly process that includes receiving at least one electronic assembly after a solder reflow process using a Sn-containing solder and a water-soluble flux. The approach includes baking the at least one electronic assembly in an oxygen containing environment and, then cleaning the at least one electronic assembly in an aqueous cleaning process.

Abstract: A nanostructure barrier for copper wire bonding includes metal grains and inter-grain metal between the metal grains. The nanostructure barrier includes a first metal selected from nickel or cobalt, and a second metal selected from tungsten or molybdenum. A concentration of the second metal is higher in the inter-grain metal than in the metal grains. The nanostructure barrier may be on a copper core wire to provide a coated bond wire. The nanostructure barrier may be on a bond pad to form a coated bond pad. A method of plating the nanostructure barrier using reverse pulse plating is disclosed. A wire bonding method using the coated bond wire is disclosed.

Abstract: A method for providing an etch mask for microelectronic processing that includes forming a material stack on a surface to be etched, wherein the material stack of at least a first material layer atop the surface to be etched for a base mandrel layer, and a second material layer atop the first material layer to provide a cap mandrel layer. If a following step, the material stack may be patterned and etched to provide double mandrel structures each including said base mandrel layer and said cap mandrel layer. A sidewall spacer is formed on sidewalls of the double mandrel structures.

Abstract: A semiconductor device includes a substrate including traces, wherein the traces protrude above a top surface of the substrate; a prefill material over the substrate and between the traces, wherein the prefill material directly contacts peripheral surfaces of the traces; a die attached over the substrate; and a wafer-level underfill between the prefill material and the die.

Abstract: In described examples, a cavity is formed between a substrate and a cap. One or more access holes are formed through the cap for removing portions of a sacrificial layer from within the cavity. A cover is supported by the cap, where the cover is for occulting the one or more access holes along a perspective. An encapsulant seals the cavity, where the encapsulant encapsulates the cover and the one or more access holes.