Abstract: A system of bonded substrates may include a first substrate, a second substrate, and a bonding layer. The first substrate may include a bonding surface, wherein a geometry of the bonding surface of the first substrate includes a plurality of microchannels. The second substrate may include a complementary bonding surface. The bonding layer may be positioned between the first substrate and the second substrate, wherein the bonding layer may fill the microchannels of the first substrate and may contact substantially the entire bonding surface of the first substrate. The bonding layer may include a metal.

Abstract: A semiconductor device, and a method of fabrication, is introduced. In an embodiment, one or more passivation layers are formed over a first substrate. Recesses are formed in the passivation layers and a first plurality of bonding pads and a second plurality of bonding pads are formed in the recesses. In an embodiment, the first plurality of bonding pads have a first width and a first pitch, and the second plurality of bonding pads have the first width and are grouped into clusters. The first plurality of bonding pads and the second plurality of bonding pads in the first substrate are aligned to a third plurality of bonding pads in a second substrate and are bonded using a direct bonding method.

Abstract: A semiconductor manufacturing method according to an embodiment includes forming a first film on a semiconductor substrate. The semiconductor manufacturing method includes forming cavities in the first film. The semiconductor manufacturing method includes forming a second film inside the cavities by a CVD method using first gas containing a component of the second film, detecting a first time point at which the second film blocks openings of the cavities in forming the second film, and ending forming of the second film at a second time point at which a predetermined time has elapsed from the first time point.

Abstract: A package has a bottomed recess with a bottom portion. The package includes: a first electrode having a first outer lead portion and disposed in the bottom portion; a second electrode having a second outer lead portion and disposed in the bottom portion; and a first resin fixing the first electrode and the second electrode and constituting a part of the bottomed recess. The first resin has: a part between the first electrode and the second electrode disposed in the bottom portion; a wall portion constituting side walls of the bottomed recess; and a flange portion having a first part located adjacent to at least one of both sides of the first outer lead portion in plan view. The first part has a thickness different from a thickness of the first outer lead portion. A light emitting has: the package; and a light emitting element mounted on at least one of the first electrode and the second electrode of the package.

Abstract: A manufacturing method of a semiconductor device according to the present embodiment includes forming a modified layer with distortion in semiconductor crystals in a first and a second semiconductor wafers by radiating laser to a dicing region of the first and second semiconductor wafers, each of the first and second semiconductor wafers including a plurality of semiconductor chips. The method also includes stacking the second semiconductor wafer on the first semiconductor wafer to be shifted in a first direction. The first direction is a direction from a first side of a first semiconductor chip of the first semiconductor wafer towards an opposite side to the first side of the first semiconductor chip. The method further includes cleaving the first and second semiconductor wafers.

Abstract: A Schottky diode includes an insulating substrate and at least one Schottky diode unit. The at least one Schottky diode unit is located on a surface of the insulating substrate. The at least one Schottky diode unit includes a first electrode, a semiconductor structure and a second electrode. The semiconductor structure comprising a first end and a second end. The first end is laid on the first electrode, the second end is located on the surface of the insulating substrate. The semiconducting structure includes a carbon nanotube structure. The second electrode is located on the second end.

Abstract: A transistor with dual spacers includes a gate, a first dual spacer and a second inner spacer. The gate is disposed on a substrate, wherein the gate includes a gate dielectric layer and a gate electrode, and the gate dielectric layer protrudes from the gate electrode and covers the substrate. The first dual spacer is disposed on the gate dielectric layer beside the gate, wherein the first dual spacer includes a first inner spacer and a first outer spacer. The second inner spacer having an L-shaped profile is disposed on the gate dielectric layer beside the first dual spacer. The present invention also provides a method of forming said transistor with dual spacers.

Abstract: A condensation reaction-type die bonding agent has little liability of poor electrical connection at the electrodes. A condensation reaction-type die bonding agent for bonding an LED device provided on its surface with device electrodes having connection surfaces covered by gold, where the die bonding agent includes (A) a polysilsesquioxane solid in state at room temperature having trisiloxy units (TA) expressed by R1SiO3/2 where, R1 indicates one group selected from the group comprised of C1 to C15 alkyl groups, a phenyl group, and a benzyl group, and having hydroxyl groups, (B) a polysilsesquioxane liquid in state at room temperature having trisiloxy units (TB) expressed by R2SiO3/2 where, R2 indicates one group selected from the group comprised of C1 to C15 alkyl groups, a phenyl group, and a benzyl group, and having —OR2 where, R2 indicates one group selected from the group comprised of C1 to C15 alkyl groups, a phenyl group, and a benzyl group, and (C) a condensation reaction catalyst.

Abstract: A method for producing an organic electroluminescent device includes the step of forming a driving circuit layer on a substrate; the step of forming an inorganic protective layer on the driving circuit layer; the step of forming an organic flattening layer on the inorganic protective layer; the step of reducing moisture contained in the organic flattening layer; the step of forming an organic electroluminescent element layer on the organic flattening layer after the step of reducing moisture; and, after the organic flattening layer is formed but before the organic flattening layer is heated, the step of forming an organic polymer film covering the organic flattening layer and the step of removing the organic polymer film.

Abstract: A transistor with dual spacers includes a gate, a first dual spacer and a second inner spacer. The gate is disposed on a substrate, wherein the gate includes a gate dielectric layer and a gate electrode, and the gate dielectric layer protrudes from the gate electrode and covers the substrate. The first dual spacer is disposed on the gate dielectric layer beside the gate, wherein the first dual spacer includes a first inner spacer and a first outer spacer. The second inner spacer having an L-shaped profile is disposed on the gate dielectric layer beside the first dual spacer. The present invention also provides a method of forming said transistor with dual spacers.

Abstract: The present disclosure relates to an integrated light emitting device. The integrated light emitting device comprises a substrate of semiconductor material, a light emitting unit integrated into the semiconductor material, and at least one cavity formed into the semiconductor material between the substrate and the light emitting unit. At least portions of the at least one cavity may be formed by Silicon-On-Nothing (SON) process steps.

Abstract: At least one conductive line in a dielectric layer over a substrate is recessed to form a channel. The channel is self-aligned to the conductive line. The channel can be formed by etching the conductive line to a predetermined depth using a chemistry comprising an inhibitor to provide uniformity of etching independent of a crystallographic orientation. A capping layer to prevent electromigration is deposited on the recessed conductive line in the channel. The channel is configured to contain the capping layer within the width of the conductive line.

Abstract: An IC fabrication system for facilitating improved thermal uniformity includes a chamber within which an IC process is performed on a substrate, a heating mechanism configured to heat the substrate, and a substrate-retaining device configured to retain the substrate in the chamber. The substrate-retaining device includes a contact surface configured to contact an edge of the retained substrate without the substrate-retaining device contacting a circumferential surface of the retained substrate. The substrate-retaining device includes a plurality of contact regions and a plurality of noncontact regions disposed at a perimeter, where the plurality of noncontact regions is interspersed with the plurality of contact regions. Each of the plurality of noncontact regions includes the contact surface.

Abstract: A electronic device module includes a first substrate; electronic devices mounted on the first substrate; a second substrate coupled to a lower surface of the first substrate, the second substrate including a device accommodating portion; a sealing portion configured to seal an electronic device in the device accommodating portion; and an external connection terminal bonded to an electrode pad disposed in a lower surface of the second substrate. Bonding surfaces of the electrode pad and the external connection terminal are disposed on a same plane as a lower surface of the sealing portion.

Abstract: A photosensitive thin film device includes a substrate that is transparent and insulative; a first electrode on the substrate; a circular semiconductor layer on the substrate and surrounding a perimeter of the first electrode; a circular second electrode on the substrate and surrounding a perimeter of the semiconductor layer; an interlayer insulating layer on the semiconductor layer and the first and second electrodes and having a first aperture exposing the first electrode; and a conductive layer including an upper surface light barrier arranged on the interlayer insulating layer and covering an upper surface of the semiconductor layer, and a contact plug extending from the upper surface light barrier and connected to the first electrode via the first aperture.

Abstract: A semiconductor structure includes a semiconductor substrate and a conductive feature formed over the semiconductor substrate, an etch stop layer formed over the conductive feature, a dielectric layer formed over the etch stop layer, a contact trench formed in the dielectric layer, a bottom of the contact trench being disposed over a top surface of the conductive feature, and a self-aligned sealing oxide layer formed on the dielectric layer. The self-aligned sealing oxide layer is conformed to sidewalls of the dielectric layer exposed in the contact trench.

Abstract: Device and method of configuring a device to process a wafer is disclosed. The device includes a wafer chuck configured to mount the wafer, a dry wafer processing chamber configured to enclose the wafer chuck, a humidity sensor configured to measure relative humidity (RH) at an outlet of the dry wafer processing chamber, a humidity controller coupled to the humidity sensor, the humidity controller being configured to detect a change in RH above a threshold, and a process chamber controller coupled to the humidity controller. The change is triggered by a leakage in deionized water used as a coolant for cooling the wafer chuck and the wafer during the processing. The process chamber controller is configured to trigger a shutdown of the processing of the wafer in response to the leakage.

Abstract: A semiconductor device includes a semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type, a first semiconductor region of a second conductivity type, a second semiconductor region of the second conductivity type, a third semiconductor region of the first conductivity type, a trench, a first electrode, and a Schottky electrode. Between trenches where the Schottky electrode is provided, a sidewall of each of the trenches is in contact with first semiconductor layer; and between trenches where the first electrode is provided, a sidewall of each of the trenches is in contact with the second semiconductor region and the third semiconductor region. A region of a part of the Schottky electrode faces toward the first semiconductor region in a depth direction and the trench faces the first semiconductor region in the depth direction.

Abstract: Provided is a semiconductor device including at least two isolation trench portions; a mesa region that is provided between the at least two isolation trench portions and includes a source region having a first conduction type, a base region having a second conduction type and at least a portion thereof provided below the source region, and a gate trench portion; and a contact layer that is an epitaxial layer provided at least in contact with side portions of the mesa region and bottom portions of the isolation trench portions positioned lower than the gate trench portion, and having a second-conduction-type impurity concentration higher than that of the base region, wherein the same impurities as in the contact layer are present in the source region, or the contact layer is provided higher than the source region.

Abstract: A FinFET including a gate stack, a semiconductor fin embedded in the gate stack, a source and a drain disposed is provided. The semiconductor fin extends along a widthwise direction of the gate stack and has a first concave and a second concave exposed at sidewalls of the gate stack respectively. The source and drain are disposed at two opposite sides of the gate stack. The source includes a first portion in contact with and embedded in the first concave. The drain includes a second portion in contact with and embedded in the second concave. The first portion and the second portion are covered by the gate stack.