Abstract: A two-type gate process is suitable for forming a gate insulation film partially formed of a high dielectric film, for example, a titanium oxide film (gate insulation film of the internal circuit) having a relative dielectric constant larger than that of silicon nitride on a substrate, and a silicon nitride film is deposited on the titanium oxide film. The silicon nitride film will prevent oxidation of the titanium oxide film when the surface of the substrate is subjected to thermal oxidation in the next process step. Next, the silicon nitride film and the titanium oxide film on the I/O circuit region are removed, while the silicon nitride film and the titanium oxide film on the internal circuit region remain, and the substrate is subjected to thermal oxidation to form a silicon oxide film as a gate insulation film on the surface of the I/O circuit region.

Abstract: This Application is intended to provide a method for effectively protecting paper or film-form media against forgery. This can be achieved by, for example, embedding in a paper or film-form medium a thin semiconductor chip up to 0.5 mm square, equipped with an antenna, and characterized in that the side walls of the semiconductor chip are formed using oxide films, and in that multiple such semiconductor chips are separated by etching. Limiting the size of these semiconductor chips to 0.5 mm or less enables improvement against bending and concentrated loads, and separating the semiconductor chips by etching results in semiconductor chips free from cracking and breakage. Also, the oxide films constituting the side walls of the semiconductor chips prevents short-circuiting at edges during connection to the respective antennas. Thus, simplified processes can be adopted.

Abstract: The present invention provides a thin film transistor, wherein the semiconductor channel region is patterned. Gate electrodes 102, gate insulating film 103, source electrodes 104, and drain electrodes 105 are formed on a glass substrate 101. A patterned insulating film is formed thereon, and a part of the film in the region 110 on the gate electrode is removed. An organic semiconductor film is formed thereon by vapor deposition. The organic semiconductor film 107 in the region 110, where the patterned insulating film is removed, becomes a channel region, and is separated from the organic semiconductor film 108 on the patterned insulating film 106. Therefore, the organic semiconductor channel region is patterned to have the same size as the gate electrode. In accordance with the present invention, a thin film transistor, wherein the semiconductor region is patterned precisely, becomes available.

Abstract: An apparatus includes a crystalline substrate having a top surface, a crystalline semiconductor layer located on the top surface, and a plurality of dielectric regions. The crystalline semiconductor layer includes group III-nitride and has first and second surfaces. The first surface is in contact with the top surface. The second surface is separated from the top surface by semiconductor of the crystalline semiconductor layer. The dielectric regions are located on the second surface. Each dielectric region is distant from the other dielectric regions and covers an end of an associated lattice defect. Each lattice defect threads the crystalline semiconductor layer.

Abstract: A semiconductor device includes a sub-collector layer, a collector layer, a base layer, an emitter layer, and an emitter cap layer, which are sequentially laminated on a substrate. It also includes an emitter electrode, a base electrode, and a collector electrode, which are respectively formed on the emitter cap layer, the base layer, and the sub-collector layer. The sub-collector layer is made up of a first sub-collector layer adjacent to the substrate and a second sub-collector layer adjacent to the collector layer. In the area between adjacent device elements, the first sub-collector layer has an element insulating region created by ion implantation, and the second sub-collector layer has a recess-shaped element insulating region.

Abstract: A vertical geometry light emitting diode is disclosed that is capable of emitting light in the red, green, blue, violet and ultraviolet portions of the electromagnetic spectrum. The light emitting diode includes a conductive silicon carbide substrate, an InGaN quantum well, a conductive buffer layer between the substrate and the quantum well, a respective undoped gallium nitride layer on each surface of the quantum well, and ohmic contacts in a vertical geometry orientation.

Abstract: The orientation ratio of a crystalline semiconductor film obtained by crystallizing an amorphous semiconductor film through heat treatment and irradiation of intense light such as laser light, ultraviolet rays, or infrared rays is enhanced, and a semiconductor device whose active region is formed from the crystalline semiconductor film and a method of manufacturing the semiconductor device are provided. In a semiconductor film containing silicon and germanium as its ingredient and having a crystal structure, the {101} plane reaches 30% or more of all the lattice planes detected by Electron backscatter diffraction.

Abstract: Packages for an integrated circuit die and methods and leadframes for making such packages are disclosed. The package includes a die, a die pad, peripheral metal contacts, bond wires, and an encapsulant. The die pad and contacts are located at a lower surface of the package. The die pad and the contacts have side surfaces which include reentrant portions and asperities to engage the encapsulant. A method of making a package includes providing a metal leadframe having a die pad in a rectangular frame. Tabs extend from the frame toward the die pad. The die pad and tabs have side surfaces with reentrant portions and asperities. A die is attached to the die pad. The die is electrically connected to the tabs. An encapsulant is applied to the upper and side surfaces of the leadframe. Finally, the leadframe is cut in situ so that the die pad and tabs are severed from the frame, the sides of the package are formed, and the package is severed from the leadframe.

Abstract: An under bump metallurgic (UBM) layer which is adapted for a chip is disclosed. The UMM layer alleviate the loss of electromigration resulting from current crowing effect at the corner of UBM layer near the transmission line. By increasing the thickness of the UBM layer at the particular region which is close to the transmission line, losses of the UBM layer due to electromigration can be compensated. The life time of the chip is, therefore, enhanced.

Abstract: A method and apparatus for depositing a low dielectric constant film by reaction of an organo silane compound and an oxidizing gas. The oxidized organo silane film has excellent barrier properties for use as a liner or cap layer adjacent other dielectric layers. The oxidized organo silane film can also be used as an etch stop or an intermetal dielectric layer for fabricating dual damascene structures. The oxidized organo silane films also provide excellent adhesion between different dielectric layers. A preferred oxidized organo silane film is produced by reaction of methyl silane, CH3SiH3, and N2O.

Abstract: In a semiconductor integrated circuit device having plural layers of buried wirings, it is intended to prevent the occurrence of a discontinuity caused by stress migration at an interface between a plug connected at a bottom thereof to a buried wiring and the buried wiring. For example, in the case where the width of a first Cu wiring is not smaller than about 0.9 ?m and is smaller than about 1.44 ?m, and the width of a second Cu wiring and the diameter of a plug are about 0.18 ?m, there are arranged two or more plugs which connect the first wirings and the second Cu wirings electrically with each other.

Abstract: A semiconductor structure and a process for fabricating the semiconductor structure. The structure includes a first and second rigid dielectric layer and a first non-rigid dielectric wiring level between such layers. The non-rigid layer includes at least one interconnect. Dummy fill shapes are associated with the non-rigid dielectric wiring level for preventing local stresses and deflections in the vicinity of the interconnect. In one aspect, the dummy fill shapes are in proximity to the interconnect which have a coefficient of thermal expansion substantially the same as the first and second rigid dielectric layer and/or provide that the average local CTE matches the CTE of the surrounding regions and the interconnect as a whole.

Abstract: A method and apparatus for a tunable optical spectrum analyzer that can measure the optical spectrum of a demultiplexed DWDM signal are presented. The signal level and Optical Signal to Noise Ratio (OSNR) of an individual channel of the DWDM signal can be obtained from the measured optical spectrum. The device employs a rapid tuning and detection technique to obtain the optical spectrum of the incoming signal. In a preferred embodiment the apparatus is fabricated on a single chip resulting in a compact measurement device. Using the device of the preferred embodiment, single channel OSNR can be determined in as small a time interval as approximately 225 microseconds. Using an array of these devices an entire DWDM mixed signal can be monitored as to OP and OSNR in the same time interval.

Abstract: A semiconductor source of emission electrons which uses a target of a wide bandgap semiconductor having a target thickness measured from an illumination surface to an emission surface. The semiconductor source is equipped with an arrangement for producing and directing a beam of seed electrons at the illumination surface and a mechanism for controlling the energy of the seed electrons such that the energy of the seed electrons is sufficient to generate electron-hole pairs in the target. A fraction of these electron-hole pairs supply the emission electrons. Furthermore, the target thickness and the energy of the seed electrons are optimized such that the emission electrons at the emission surface are substantially thermalized. The emission of electrons is further facilitated by generating negative electron affinity at the emission surface. The source of the invention can take advantage of diamond, AlN, BN, Ga1-yAlyN and (AlN)x(SiC)1-x, wherein 0?y?1 and 0.2?x?1 and other wide bandgap semiconductors.

Abstract: An electrically programmable fuse includes a metal-oxide-semiconductor (MOS) programmable transistor that is gate-source coupled by a resistive element. The resistive element can comprise a gate-source coupled MOS transistor. If the MOS transistor is unprogrammed, then the resistive element ensures that the programmable transistor is turned off during read operations. However, when a programming voltage is applied across the source and drain terminals of the programmable transistor, the resistive element allows the programming voltage to be capacitively coupled to the gate of the programmable transistor from its drain. This turns the programmable transistor on, thereby reducing the snapback voltage of the programmable transistor, and hence, the required programming voltage. Once the snapback mode is entered, current flow through the programmable transistor increases until thermal breakdown occurs and the programmable transistor shorts out.

Abstract: A clip is used to clamp a LED in place in a LED module. The clip has pliable conducting cover and can be latched to the upper lead metal of the LED module. The clip can be lifted for replacing a defective or color LED. A plurality of replaceable LEDs can be mounted a common metal substrate to form a display panel, and each LED can be clamped in position with clips straddling between parallel upper lead metal for electrical coupling to the top electrodes of the LED.

Abstract: A package for a surface-emitting laser encloses the die between a sub-mount and a cap. The sub-mount and the cap can be formed using wafer processing techniques that permit a wafer level packaging process which attaches multiple die to a sub-mount wafer, attaches caps either separated or as part of a cap wafer to the sub-mount wafer, and cuts the structure to separate individual packages. The cap includes a transparent plate that can be processed to incorporate an optical element such as a lens. An alignment post attached to the cap indicates the position of an optical signal from the laser and fits snugly into one end of a sleeve while an optical fiber connector fits into the other end.

Abstract: A nonvolatile semiconductor memory device according to the present invention has a control gate electrode which is formed on the upper stage of a stepped portion formed in the principal surface of a substrate with a first insulating film interposed therebetween and a floating gate electrode which is formed to cover up the stepped portion, capacitively coupled to the side surface of the control gate electrode closer to the stepped portion with a second insulating film interposed therebetween, and opposed to the lower stage of the stepped portion with a third insulating film serving as a tunnel film interposed therebetween.

Abstract: In one embodiment, a lateral FET structure (30) is formed in a body of semiconductor material (32). The structure (30) includes a plurality non-interdigitated drain regions (39) that are coupled together with a conductive layer (57), and a plurality of source regions (34) that are coupled together with a different conductive layer (51). One or more interlayer dielectrics (53,54) separate the two conductive layers (51,57). The individual source regions (34) are absent small radius fingertip regions.

Abstract: This invention relates to a light-receiving module in which transmission impedance of lead terminals are matched by simple method. The module has a semiconductor light-receiving device, such as a photo diode, a plurality of lead terminals for transmitting an electrical signal converted by the semiconductor device, and a metal base with a plurality of through holes, the lead terminals passes therethrough. The diameter of the lead terminal for signal transmission is smaller as compared with that of other lead terminal and the diameter of the through holes is adjusted and filled by a sealant glass with a dielectric constant so as to match the impedance thereof.