Abstract: The invention relates to a substrate for a display, a method of manufacturing the same, and a display having the same and provides a substrate for a display which can be manufactured through simple steps with high reliability, a method of manufacturing the same, and a display having the same. The substrate is configured to have a gate bus line, an OC layer formed on the gate bus line, a pixel electrode formed on the OC layer at each pixel region, and a gate terminal for electrically connecting an external circuit and the gate bus line.

Abstract: A foam-holding body 52 having a large difference in refractive index between foams 521 and the surrounding material is disposed on the major light extraction surface of the sapphire substrate 50. The foam-holding body 52 has translucency to light of a light-emitting wavelength and is formed of a material such as a silicone or the like, having a refractive index equal to or more than 1.77, and includes a foam-holding layer holding a plurality of foams made of an air or an inactive gas having a refractive index of about one. Therefore, when the light emitted in the light-emitting portion scatters in the foam-holding body 52, the spread of the scattered light becomes wide, which restricts repetition of the total reflection in the light-emitting device to improve an efficiency of the light extraction.

Abstract: In one embodiment a method is provided. The method comprises inserting a first end of a P-type semiconductor pin in a first through hole via in a substrate; inserting a first end of an N-type semiconductor pin in a second through hole via in the substrate; and electrically connecting the first ends of the P and N-type semiconductor pins to form a precursor Peltier cooling device which in cooperation with a semiconductor die, bridges the P and N-type semiconductor pins between their ends remote from the first ends to define a Peltier cooling device in the substrate.

Abstract: To realize an area reduction of a semiconductor chip without adding a process, and to provide a semiconductor chip structure having an excellent pressure balance when mounted. In the structure of a semiconductor chip in which control/power supply lines are formed on a glass substrate, connecting terminals for electrically connecting with the control/power supply lines are provided in alignment in the longitudinal direction of the semiconductor device, whereby the wiring length within the semiconductor chip can be suppressed to be minimum. Since the wiring length is shortened, the width of the wirings within the semiconductor chip is narrowed, so that the area of the semiconductor chip is reduced.

Abstract: A thin film transistor having a LDD structure that may improve its channel reliability and output characteristics. A semiconductor layer comprises source/drain regions, a channel region positioned between the source/drain regions, and an LDD region positioned between the channel region and a source/drain region, wherein a projected range of ions doped on the semiconductor layer extends to a first depth from the surface of the semiconductor layer in the LDD region.

Abstract: A process for manufacturing a phase change memory cell, comprising the steps of: forming a resistive element; forming a delimiting structure having an aperture over the resistive element; forming a memory portion of a phase change material in the aperture, the resistive element and the memory portion being in direct electrical contact and defining a contact area of sublithographic extension. The step of forming a memory portion further includes filling the aperture with the phase change material and removing from the delimiting structure an exceeding portion of the phase change material exceeding the aperture.

Abstract: A semiconductor light-emitting device includes a semiconductor light-emitting thin film, the thickness h of which satisfies the following conditional equation: 0.9 × ( 2 ? m + 1 ) ? ? 0 4 ? n ? h ? 1.1 × ( 2 ? m + 1 ) ? ? 0 4 ? n and m in the conditional equation satisfies the following conditional equation: 2 ? m + 1 m ? ( m + 1 ) ? ? 0 2 > ? where ?0 is a center wavelength of light generated in the semiconductor light-emitting thin film, n is a refractive index of the semiconductor light-emitting thin film, m is 0 or a positive integer, and ? is a half bandwidth of a light emission spectrum when there is no interference between light rays generated in the semiconductor light-emitting thin film.

Abstract: Isolation methods and devices for isolating regions of a semiconductor device. The isolation method and structure include forming an isolating trench in an active area and filling the trench with a doped conductive material containing silicon. Suitable conductive materials containing silicon include polysilicon and silicon-germanium. There is also provided a method and structure for isolating the regions by providing a trench in an active area of a substrate, growing an epitaxial layer in the trench to fill the trench or to partially fill the trench and depositing an insulating material over the epitaxial layer and within the trench to completely fill the trench.

Abstract: In a semiconductor device, a wiring pattern groove is formed in a surface portion of a silicon oxide film provided above a semiconductor substrate. A wiring layer is buried into the wiring pattern groove with a barrier metal film interposed therebetween. The barrier metal film is selectively removed from each sidewall portion of the wiring pattern groove. In other words, the barrier metal film is left only on the bottom of the wiring pattern groove. Thus, a damascene wiring layer having a hollow section whose dielectric constant is low between each sidewall of the wiring pattern groove and each side of the wiring layer can be formed in the semiconductor device.

Abstract: Techniques for forming devices, such as transistors, having vertical junction edges. More specifically, shallow trenches are formed in a substrate and filled with an oxide. Cavities may be formed in the oxide and filled with a conductive material, such a heavily doped polysilicon. Vertical junctions are formed between the polysilicon and the exposed substrate at the trench edges such that during a thermal cycle, the heavily doped polysilicon will out-diffuse doping elements into the adjacent single crystal silicon advantageously forming a diode extension having desirable properties.

Abstract: A semiconductor light emitting device includes a mold resin having a cup shape portion on an upper surface of the mold resin. One or more holes penetrate through the cup shape portion to outside of the mold resin and/or one or more trenches extend from the cup-shaped portion to outside the mold resin. A first lead is provided in the mold resin and extending from the cup shape portion to outside of the mold resin in a first direction, and a second lead provided in the mold resin and extending from the cup shape portion to outside of the mold resin in a second direction which is opposite to the first direction. A light emitting element is mounted on the first lead in the cup shape portion, and a wire electrically connects the light emitting element and the second lead. A sealing resin is embedded in the one or more holes and the one or more trenches and is configured to seal the light emitting element and the wire.

Abstract: An epitaxial silicon carbide layer is fabricated by forming first features in a surface of a silicon carbide substrate having an off-axis orientation toward a crystallographic direction. The first features include at least one sidewall that is orientated nonparallel (i.e., oblique or perpendicular) to the crystallographic direction. A first epitaxial silicon carbide layer is then grown on the surface of the silicon carbide substrate that includes first features therein. Second features are then formed in the first epitaxial layer. The second features include at least one sidewall that is oriented nonparallel to the crystallographic direction. A second epitaxial silicon carbide layer is then grown on the surface of the first epitaxial silicon carbide layer that includes the second features therein.

Abstract: A technique for and structures for camouflaging an integrated circuit structure. The technique includes the use of a light density dopant (LDD) region of opposite type from the active regions resulting in a transistor that is always off when standard voltages are applied to the device.

Abstract: According to some embodiments, a semiconductor device includes a lower semiconductor substrate, an upper silicon pattern, and a MOS transistor. The MOS transistor includes a body region formed within the upper silicon pattern and source/drain regions separated by the body region. A buried insulating layer is interposed between the lower semiconductor substrate and the upper silicon pattern. A through plug penetrates the buried insulating layer and electrically connects the body region with the lower semiconductor substrate, the through plug positioned closer to one of the source/drain regions than the other source/drain region. At least some portion of the upper surface of the through plug is positioned outside a depletion layer when a source voltage is applied to the one of the source/drain regions, and the upper surface of the through plug is positioned inside the depletion layer when a drain voltage is applied to the one region.

Abstract: An integrated optical device allowing for higher flexibility in designing its outer shape and securing hermetic sealing is provided, which includes a ceramic substrate mounting a light source, a covering member fixed to the substrate for covering the light source, and a resin mold package for attaching the substrate, wherein a metal joint portion on the substrate and a metal joint portion on the covering member are joined, as well as a through-hole in the substrate or in covering member is sealed with a transparent material for hermetic sealing of the light source.

Abstract: A plurality of gate lines having gate electrodes are formed on a substrate and a semiconductor layer is formed on a gate insulating layer covering the gate lines. A plurality of data lines intersecting the gate lines are formed on the gate insulating layer and a plurality of drain electrodes are formed extending parallel with and adjacent to the data lines. Furthermore, a plurality of storage capacitor conductors are formed to be connected to the drain electrodes and to overlap an adjacent gate line. A passivation layer made of an organic material is formed on the above structure and has a contact hole. Furthermore, a plurality of pixel electrodes are formed to be electrically connected to the drain electrodes through the contact hole.

Abstract: First alignment marks are provided on a film substrate in a manner that they are located at positions offset from the disposed positions of second alignment marks provided on a semiconductor chip. The amount of expansion or contraction of the film substrate is obtained by measuring the distance between the first alignment marks. Based on the amount of expansion or contraction, the semiconductor chip is shifted with respect to the film substrate and mounted thereon.

Abstract: The invention relates to a high power LED package, in which a package body is integrally formed with resin to have a recess for receiving an LED chip. A first sheet metal member is electrically connected with the LED chip, supports the LED chip at its upper partial portion in the recess, is surrounded by the package body extending to the side face of the package body, and has a heat transfer section for transferring heat generated from the LED chip to the metal plate of the board and extending downward from the inside of the package body so that a lower end thereof is exposed at a bottom face of the package body thus to contact the board. A second sheet metal member is electrically connected with the LED chip spaced apart from the first sheet metal member for a predetermined gap, and extends through the inside of the package body to the side face of the package body in a direction opposite to the first sheet metal member. A transparent sealant is sealingly filled up into the recess.

Abstract: In photonic integrated circuits (PICs) having at least one active semiconductor device, such as, a buried heterostructure semiconductor laser, LED, modulator, photodiode, heterojunction bipolar transistor, field effect transistor or other active device, a plurality of semiconductor layers are formed on a substrate with one of the layers being an active region. A current channel is formed through this active region defined by current blocking layers formed on adjacent sides of a designated active region channel where the blocking layers substantially confine the current through the channel. The blocking layers are characterized by being an aluminum-containing Group III-V compound, i.e., an Al-III-V layer, intentionally doped with oxygen from an oxide source. Also, wet oxide process or a deposited oxide source may be used to laterally form a native oxide of the Al-III-V layer.

Abstract: An LED includes a semiconductor region having an active layer sandwiched between two confining layers of opposite conductivity types for generating heat. A cathode is arranged centrally on one of the opposite major surfaces of the semiconductor region from which is emitted the light. Attached to the other major surface of the semiconductor region, via an ohmic contact layer, is a reflective metal layer for reflecting the light that has traversed the ohmic contact layer, back toward the semiconductor region. A transparent antidiffusion layer is interposed between the ohmic contact layer and the reflective layer in order to prevent the ohmic contact layer and the reflective layer from thermally diffusing from one into the other to the impairment of the reflectivity of the reflective layer.