Abstract: An ultraviolet type white color light emitting device (Q) including a 340 nm–400 nm ultraviolet InGaN-LED, a first fluorescence plate of ZnS doped with more than 1×1017cm?3 Al, In, Ga, Cl, Br or I for absorbing ultraviolet rays and producing blue light (fluorescence), a second fluorescence plate of ZnSSe or ZnSe doped with more than 1×1017 cm?3 Al, In, Ga, Cl, Br or I for absorbing the blue light, producing yellow light (fluorescence) and synthesizing white color light by mixing the yellow light with the blue light. A blue light type white color light emitting device (R) including a 410 nm–470 nm blue light InGaN-LED, a fluorescence plate of ZnSxSe1-x (untreated 0.2?x?0.6; heat-treated 0.3?x?0.67) doped with more than 1×1017 cm?3 Al, In, Ga, Cl, Br or I for absorbing the blue light, producing 568 nm–580 nm yellow light (fluorescence) and synthesizing white color light by mixing the yellow light with the blue LED light.

Abstract: In photonic integrated circuits (PICs) having at least one active semiconductor device, such as, a buried heterostructure semiconductor laser, LED, modulator, photodiode, heterojunction bipolar transistor, field effect transistor or other active device, a plurality of semiconductor layers are formed on a substrate with one of the layers being an active region. A current channel is formed through this active region defined by current blocking layers formed on adjacent sides of a designated active region channel where the blocking layers substantially confine the current through the channel. The blocking layers are characterized by being an aluminum-containing Group III-V compound, i.e., an Al-III-V layer, intentionally doped with oxygen from an oxide source. Also, wet oxide process or a deposited oxide source may be used to laterally form a native oxide of the Al-III-V layer.

Abstract: The present invention provides a semiconductor device wherein the area of a peripheral circuit region with respect to a pixel region is reduced, and provides a manufacturing method of the semiconductor device. A semiconductor device according to the present invention is characterized by having a pixel region 1, peripheral circuit regions 2a to 2c arranged in at least a part of the periphery of the pixel region, and a wiring formed in the peripheral circuit region, and by having a wiring multilayered with two or more layers. At least one layer of the multilyered wiring is formed from a low resistance material. Transistors are formed in the peripheral circuit region, and the multilayer wiring with two or more layers is formed on the upper side of the transistors.

Abstract: Systems and methodologies are provided for simplifying a polymer memory cell's operation by employing a post polymer growth treatment to form ionic or super ionic metal compounds therein. Such post polymer growth treatment facilitates distribution and mobility of metal ions (or charged metallic molecules) within an active layer of the polymer memory cell, and mitigates (or eliminates) a need for initialization procedures. Moreover, the post treatment of the present invention can also facilitate controlling a distribution of various thresholds (e.g., write and erase threshold), and set them to predetermined values Accordingly, variability in threshold values of polymer memory cells that can result from initialization processes can be mitigated (or eliminated), and thicker polymer layers can be employed without an initialization penalty.

Abstract: A semiconductor device (21) can include, e.g., a recessed portion (25) on the reverse surface (224) of an insulating resin (22) which is the mounting surface of the semiconductor device (21). Additionally, on the outer peripheral surface of the recessed portion (25), the exposed region of leads (26) and the reverse surface (224) of the insulating resin (22) form generally the same plane. This allows, e.g., a QFN semiconductor device (21) according to preferred embodiments herein to place dust particles in the recessed portion (25) even in the presence of dust particles such as crushed burr particles of the leads (26) or plastic burrs, thereby avoiding mounting deficiencies when mounting the semiconductor device.

Abstract: A dual-sided semiconductor device is formed on a wafer with a resistive element that is formed through the wafer. By forming the resistive element through the wafer, a resistive element, such as a large resistive element, can be formed on the wafer that requires very little silicon surface area.

Abstract: A high resistance region may be used to isolate the body of a first transistor from a body contact.

Abstract: A microelectronic package includes a microelectronic element having contacts accessible at a surface thereof, a layer overlying the microelectronic element, the layer having a first surface and a sloping peripheral edge extending away from the first surface of the layer, and conductive terminals overlying the microelectronic element, wherein the layer supports the conductive terminals over the microelectronic element. The package also includes conductive traces having first ends electrically connected with the contacts of the microelectronic element and second ends electrically connected with the conductive terminals, with at least one of the conductive traces having a section that is in contact with and extends along the sloping peripheral edge of the layer, and a compliant material disposed between the conductive terminals and the microelectronic element so that the conductive terminals are movable relative to the microelectronic element.

Abstract: A flip chip type of light-emitting semiconductor device using group III nitride compound includes a thick positive electrode. The positive electrode, which is made of at least one of silver (Ag), rhodium (Rh), ruthenium (Ru), platinum (Pt) and palladium (Pd), and an alloy including at least one of these metals, is adjacent to a p-type semiconductor layer, and reflect light toward a sapphire substrate. Accordingly, a positive electrode having a high reflectivity and a low contact resistance can be obtained. A first thin-film metal layer, which is made of cobalt (Co) and nickel (Ni), or any combinations of including at least one of these metals, formed between the p-type semiconductor layer and the thick electrode, can improve an adhesion between an contact layer and the thick positive electrode. A thickness of the first thin-film metal electrode should be preferably in the range of 2 ? to 200 ?, more preferably 5 ? to 50 ?. A second thin-film metal layer made of gold (Au) can further improve the adhesion.

Abstract: An epitaxial silicon carbide layer is fabricated by forming first features in a surface of a silicon carbide substrate having an off-axis orientation toward a crystallographic direction. The first features include at least one sidewall that is orientated nonparallel (i.e., oblique or perpendicular) to the crystallographic direction. A first epitaxial silicon carbide layer is then grown on the surface of the silicon carbide substrate that includes first features therein. Second features are then formed in the first epitaxial layer. The second features include at least one sidewall that is oriented nonparallel to the crystallographic direction. A second epitaxial silicon carbide layer is then grown on the surface of the first epitaxial silicon carbide layer that includes the second features therein.

Abstract: A flip chip light-emitting diode package comprising a Schottky diode group, a light-emitting diode and a plurality of bumps is provided. The Schottky diode group comprises a plurality of Schottky diodes electrically coupled in series or in parallel. The bumps are disposed between one of the Schottky diodes and the light-emitting diode so that the Schottky diode group and the light-emitting diode are connected reverse and in parallel. The light-emitting diode is disposed on one of the Schottky diodes and connected together by a flip-chip bonding process. The flip chip light-emitting diode package prevents damaging from electrostatic discharge and promotes light extraction efficiency. In addition, the submount of the Schottky diode is fabricated by using silicon material. Since silicon is an excellent material for heat dissipating, light extraction efficiency and reliability of the package is increased.

Abstract: A hybrid orientation semiconductor structure and method of forming the same. The structure includes (a) a semiconductor substrate comprising a first semiconductor material having a first lattice orientation; (b) a back gate region on the semiconductor substrate; (c) a back gate dielectric layer on the back gate region; (d) a semiconductor region on the back gate dielectric layer, wherein the semiconductor region is electrically insulated from the back gate region by the back gate dielectric layer, and wherein the semiconductor region comprises a second semiconductor material having a second lattice orientation different from the first lattice orientation; and (e) a field effect transistor (FET) formed on the semiconductor region, wherein changing a voltage potential applied to the back gate region causes a change in a threshold voltage of the FET.

Abstract: In an electronic device comprising a first electrodes consisting of a metal oxide and a second electrode consisting of an aluminum alloy film directly contacted and electrically connected to the first electrode, the contact interface between the aluminum alloy film and the first electrode is constructed so that at least a part of alloy components constituting the aluminum alloy film exist as a precipitate or concentrated layer. This construction enables direct contact between the aluminum alloy film and the electrode consisting of a metallic oxide and allows elimination of a barrier metal in such an electronic device, and manufacturing technology therefor.

Abstract: A unit according to the present invention includes a substrate and an IC chip used for driving a light-emitting device. A relay terminal is provided at a region spaced from peripheral areas of the substrate so as to connect the light-emitting device with the IC chip. The relay terminal is connected with a corresponding terminal of the IC chip via a connecting channel such as wire-bonding. The light-emitting device is supported by the substrate such that a terminal of the light-emitting device is electrically connected with the relay terminal. A length of a wiring line between the light-emitting device for an optical pick-up and the unit used for driving the light-emitting device is decreased.

Abstract: A light emitting diode (LED) packaging comprising a stacked substrate, a main body, and an LED die is provided. The stacked substrate includes a heat spreader and a first circuit board. The first circuit board is stacked on the heat spreader. Two channels penetrate the first circuit board and the heat spreader. An upper opening of the channel is smaller than a lower opening thereof. The main body is formed on the first circuit board and has a through hole to expose part of the first circuit board. The main body further has at least two extended portion filling the channels for fixing the main body on the stacked substrate. The LED die is located in the through hole and electrically connected to the first circuit board.

Abstract: A semiconductor device includes a substrate, and a semiconductor thin film bonded to the substrate, wherein the semiconductor thin film includes a plurality of discrete operating regions and an element isolating region which isolates the plurality of discrete operating regions, and the element isolating region is etched to a shallower depth than a thickness of the semiconductor thin film, and is a thinner region than the plurality of discrete operating regions.

Abstract: There are provided a semiconductor device and method for fabricating the device capable of achieving reliable electrical connection by securely directly bonding conductors to each other even though bonding surfaces are polished by a CMP method and solid-state-bonded to each other. By polishing according to the CMP method, a through hole conductor 5 and a grounding wiring layer 10, which are made of copper, become concave in a dish-like shape and lowered in level, causing a dishing portion 17 since they have a hardness lower than that of a through hole insulator 11 made of silicon nitride. The through hole insulator 11 is selectively etched by a reactive ion etching method until the through hole insulator 11 comes to have a height equal to the height of a bottom portion 19 of the dishing portion 17 of the through hole conductor 5. The through hole conductors 5 and 25 are aligned with each other, and the bonding surfaces 12 and 22 are bonded to each other in a solid state bonding manner.

Abstract: Electrostatic discharge (ESD) devices for protection of integrated circuits are described. ESD devices may be configured to provide uniform breakdown of finger regions extending through a first region of a substrate having a first conductivity type and into a second region of the substrate more lightly doped with impurities of the first conductivity type. Such an EDS device may include a collector region having a middle region highly doped with impurities of the first conductivity type. The middle region may be proximate to a layer that is lightly doped with impurities of the first conductivity type and a layer that is doped with impurities of the second conductivity type. The collector region may decrease the breakdown voltage of the EDS device. The lightly doped region may be eliminated in the collector region and an interlayer insulating layer is formed in contact with the top side regions and the middle region.

Abstract: The invention includes a method of forming a semiconductor construction. A semiconductor substrate is provided, and a conductive node is formed to be supported by the semiconductor substrate. A first conductive material is formed over the conductive node and shaped as a container. The container has an opening extending therein and an upper surface proximate the opening. The container opening is at least partially filled with an insulative material. A second conductive material is formed over the at least partially filled container opening and physically against the upper surface of the container. The invention also includes semiconductor structures.

Abstract: Packages for an integrated circuit die and methods and leadframes for making such packages are disclosed. The package includes a die, a die pad, peripheral metal contacts, bond wires, and an encapsulant. The die pad and contacts are located at a lower surface of the package. The die pad and the contacts have side surfaces which include reentrant portions and asperities to engage the encapsulant. A method of making a package includes providing a metal leadframe having a die pad in a rectangular frame. Tabs extend from the frame toward the die pad. The die pad and tabs have side surfaces with reentrant portions and asperities. A die is attached to the die pad. The die is electrically connected to the tabs. An encapsulant is applied to the upper and side surfaces of the leadframe. Finally, the leadframe is cut in situ so that the die pad and tabs are severed from the frame, the sides of the package are formed, and the package is severed from the leadframe.