Abstract: A method of forming a semiconducting wafer is provided that utilizes fewer processing operations, reduces process variation, and lowers cost as well as production time. The method provided further improves via reliability by permitting vias to be formed with consistent aspect ratios. Devices and method are provided that substantially eliminate four way intersections on semiconductor wafers between conducting elements and supplemental elements. The devices and methods provide a more uniform deposition rate of a subsequent dielectric layer. Four way intersections are removed from both conductive element regions as well as supplemental element regions.

Abstract: A ultrathin magnetoelectric transducer and its manufacturing method are provided which enable the quality of mounting to be inspected nondestructively, and can reduce a footprint. The magnetoelectric transducer has a substrate composed of a nonmagnetic substrate, and includes bottom surface connecting electrodes whose leads have a first thickness, and side electrodes which are exposed by dicing and have the first thickness. A more sensitive Hall element has a high-permeability magnetic substrate as the substrate, and includes the bottom surface connecting electrodes whose leads have the first thickness, and the side electrodes exposed by the dicing and having the first thickness. The bottom surface connecting electrodes of the leads with the first thickness are formed across the internal electrodes of adjacent magnetoelectric transducers with maintaining the first thickness. The side electrodes with the first thickness are formed by cutting the center between the adjacent magnetoelectric transducers.

Abstract: An array of multi-level non-volatile memory transistors features a transistor construction with a conductive polysilicon control gate having opposed sidewalls insulatively spaced just above the substrate. Conductive polysilicon spacers are separated from the opposed sidewalls by thin tunnel oxide. Source and drain implants are beneath or slightly outboard of the spacers. Insulative material is placed over the structure with a hole cut above the control gate for contact by a gate electrode connected to, or part of, a conductive word line. The array has auxiliary low voltage transistors which may be made at the same time as the formation of the memory transistors. The auxiliary transistors apply opposite phase clock pulses to source and drain electrodes of transistors in the array so that first one side of each memory transistor may be written to, or read, then the other side.

Abstract: The object is to provide a lightened semiconductor device and a manufacturing method thereof by pasting a layer to be peeled to various base materials. In the present invention, a layer to be peeled is formed on a substrate, then a seal substrate provided with an etching stopper film is pasted with a binding material on the layer to be peeled, followed by removing only the seal substrate by etching or polishing. The remaining etching stopper film is functioned as a blocking film. In addition, a magnet sheet may be pasted as a pasting member.

Abstract: In a thin film semiconductor device realized on a flexible substrate, an electronic device using the same, and a manufacturing method thereof, the thin film semiconductor device and an electronic device include a flexible substrate, a semiconductor chip, which is formed on the flexible substrate, and a protective cap, which seals the semiconductor chip. Durability of the thin film semiconductor device against stress due to bending of the substrate is improved by using the protective cap.

Abstract: Arrangements are provided to effectively prevent wire disconnection generated due to an increase of heat applied to a semiconductor integrated circuit device The semiconductor integrated circuit device is structured such that a metal layer containing a Pd layer is provided in a portion to which a connecting member having a conductivity is connected, and an alloy layer having a melting point higher than that of an Sn—Pb eutectic solder and containing no Pb as a main composing metal is provided outside a portion molded by a resin. Further, a metal layer in which a thickness in a portion to which the connecting member having the conductivity is adhered is equal to or more than 10 ?m is provided in the connecting member.

Abstract: An LED package comprises a substrate, one or three terminals formed on a first side of the substrate, three terminals formed on a second side opposite to the first side, and two or three LEDs disposed on the substrate, one of the LEDS being electrically connected to one of the terminals formed on the first side while being electrically connected to one of the terminals formed on the second side, and other LEDS being electrically connected to two terminals formed on the first side or to two terminals formed on the second side. A light source comprises the LED packages having the structure as described above. Without being arranged in a line, the LEDs emitting the same color are differently arranged in every LED package, thereby solving the problem of non-uniform combination of the colors according to the positions of the LEDs on an LED package-mounting substrate.

Abstract: Disclosed are a phase-change memory device and its manufacturing method, which can reduce a contact area between a bottom electrode and a phase-change layer, thereby reducing the quantity of current necessary for phase change. The phase-change memory device comprises: a first oxide layer formed on a dielectric interlayer and a bottom electrode on a substrate and having a contact hole for exposing the bottom electrode formed in the first oxide layer; a spacer formed on a side surface of the contact hole; a phase-change layer formed on the spacer and the bottom electrode while forming a shape of another spacer; a second oxide layer filling in the contact hole while exposing an upper portion of the phase-change layer; and a top electrode formed on the first oxide layer while being in contact with the upper portion of the phase-change layer.

Abstract: A semiconductor laser device aimed to be reduced in size and that can maintain high position accuracy, and a fabrication method of such a semiconductor laser device are achieved. A semiconductor laser device includes a stem as a base member, and a cap member. The stem includes a main unit having a reference plane, and a heat sink platform as an element mount unit, located on the reference plane for mounting a laser element. The cap member is set on the reference plane of the stem so as to cover the heat sink platform. A hole is formed at the sidewall of the cap member facing the heat sink platform. Fixation between the cap member and the stem is established by fixedly attaching the portion at the inner side of the sidewall of the cap member adjacent the hole to the outer circumferential plane of a heat sink platform.

Abstract: A nitride-based semiconductor light-emitting device includes a light-emitting element having an n-GaN substrate and a nitride-based semiconductor multilayer film formed on the n-GaN substrate. The n-GaN substrate of the light-emitting element is fixed to a mount surface. The n-GaN substrate has one surface with the nitride-based semiconductor multilayer film formed thereon and an opposite surface with a metal layer and an ohmic electrode formed thereon. The metal layer contains a first metal and a second metal and the ohmic electrode is formed of the second metal. The adhesion between the ohmic electrode and the n-GaN substrate is thus improved. Accordingly, the semiconductor light-emitting device which is highly reliable with respect to the thermal strain from the mount surface can be provided.

Abstract: There has been a problem that the manufacturing process is complicated and the number of processes is increased when a TFT with an LDD structure or a TFT with a GOLD structure is formed. In a method of manufacturing a semiconductor device, after low concentration impurity regions (24, 25) are formed in a second doping process, a width of the low concentration impurity region which is overlapped with the third electrode (18c) and a width of the low concentration impurity region which is not overlapped with the third electrode can be freely controlled by a fourth etching process. Thus, in a region overlapped with the third electrode, a relaxation of electric field concentration is achieved and then a hot carrier injection can be prevented. And, in the region which is not overlapped with the third electrode, the off-current value can be suppressed.

Abstract: A material including a glass or vitroceramic substrate having a first layer and a second layer deposited thereon, each of the first and second layers including at least one transparent conducting oxide (TCO). The first layer has a roughness of more than 1 nm and the second layer has a roughness less than or equal to 1 nm. A transmittance in the visible wavelength range of the material is at least 80%. The work function of the second layer is greater than the work function of the first layer and is greater than 4.6 eV.

Abstract: In an electronic device comprising a first electrodes consisting of a metal oxide and a second electrode consisting of an aluminum alloy film directly contacted and electrically connected to the first electrode, the contact interface between the aluminum alloy film and the first electrode is constructed so that at least a part of alloy components constituting the aluminum alloy film exist as a precipitate or concentrated layer. This construction enables direct contact between the aluminum alloy film and the electrode consisting of a metallic oxide and allows elimination of a barrier metal in such an electronic device, and manufacturing technology therefor.

Abstract: A method of a bulk tri-gate transistor having stained enhanced mobility and its method of fabrication. The present invention is a nonplanar transistor having a strained enhanced mobility and its method of fabrication. The transistor has a semiconductor body formed on a semiconductor substrate wherein the semiconductor body has a top surface on laterally opposite sidewalls. A semiconductor capping layer is formed on the top surface and on the sidewalls of the semiconductor body. A gate dielectric layer is formed on the semiconductor capping layer on the top surface of a semiconductor body and is formed on the capping layer on the sidewalls of the semiconductor body. A gate electrode having a pair of laterally opposite sidewalls is formed on and around the gate dielectric layer. A pair of source/drain regions are formed in the semiconductor body on opposite sides of the gate electrode.

Abstract: A light-emitting diode (LED) structure with electrostatic discharge (ESD) protection is described. The LED includes a substrate, a patterned semiconductor layer, a first electrode and a second electrode. The patterned semiconductor layer is disposed over the substrate, and is divided into at least a first island structure and a second island structure. The first electrode and the second electrode are connected between the first island structure and the second island structure. A shunt diode is formed by the first electrode, the second electrode and the second island structure. The shunt diode is connected in parallel to the LED with an inverse voltage compared to the LED. In the LED structure of the invention, the first island structure and the second island structure are manufactured simultaneously by the epitaxy procedure. Therefore, the LED could be protected from damage due to electrostatic discharge (ESD).

Abstract: A semiconductor device can include a channel including a zinc-indium oxide film.

Abstract: A luminous lamination structure includes a first layer made of n-type nitride semiconductor and a second layer made of p-type nitride semiconductor and disposed over the first layer wherein a luminous region is defined between the first and second layers. The second layer is removed to expose the first layer in a first area which is a partial surface of the first layer. A p-side electrode is disposed on a surface of the second layer and electrically connected to the second layer. An insulating film covers the p-side electrode. An n-side electrode electrically connected to the first layer is disposed in the first area. A reflection film disposed on the insulating film extends to the n-side electrode and electrically connected to the n-side electrode. The reflection film is made of silver containing alloy or silver.

Abstract: A semiconductor memory comprises: a fist conductivity type semiconductor substrate and one or more memory cells constituted of an island-like semiconductor layer, a charge storage layer and a control gate, the charge storage layer and the control gate being formed to entirely or partially encircle a sidewall of the island-like semiconductor layer, wherein at least one of said one or more memory cells is electrically insulated from the semiconductor substrate.

Abstract: A pixel structure and an edge-emitter field-emission display device having a first substrate or backplate including a cathode disposed thereon and a second substrate or faceplate including an anode disposed thereon, wherein the anode on the second substrate or faceplate has a light emitting film. The cathode may define a first bus of an X-Y bus array and the anode may define a second bus of the X-Y bus array. Alternatively, the first substrate may further include a control gate disposed thereon, wherein the cathode defines a first bus of an X-Y bus array and the control gate defines a second bus of the X-Y bus array.

Abstract: The problem is to provide a technology to reduce a light leakage current in order to obtain a good display. One kind or plurality kinds of elements chosen from argon, germanium, silicon, helium, neon, krypton, and xenon are implanted in a crystalline semiconductor layer, to distribute crystal defects due to the aforementioned element implantation by uniform and suitable density in the semiconductor film, making recombination centers of carriers, to thereby suppress alight sensitivity without spoiling a high degree of carrier movement included in a crystalline semiconductor layer.