Abstract: Methods and apparatus are provided for controlling writing and reading of data in an array of A storage fields of a probe-based data storage device in which data is written to and read from the array of storage fields by a corresponding array of probes. One method provides error-tolerance by exploiting the inherent parallelism of the probe storage array. A user data block to be written to the A-field array is first coded to produce a plurality of C-byte codewords, such that r.C=k1.A where r is the number of codewords and k1 is an integer?1. A sub-blocks of k1 bytes are produced from the codewords by selecting successive bytes of each sub-block cyclically from the r codewords. The A sub-blocks are then written via respective probes to the corresponding storage fields of the storage field array.

Abstract: A system for generating CRC code words associated with data ranging up to w-bytes in width. The system is an iterative approach for providing a CRC calculation circuitry with the CRC calculation being subdivided into a blocks with selectable bus widths which blocks can be cascaded to provide calculation for a parallel bus width of any arbitrary number of bytes. The circuitry includes a first plurality of serially coupled code-generation blocks each for generating a CRC value based on data input to each block; a second plurality of parallel coupled code-generation blocks each for generating a CRC value based on data inputs, and, a device for selecting particular CRC code generation blocks in the first and second pluralities to be included in a CRC calculation based on the data input such that any number of data input bytes may be processed.

Abstract: Data processing and transmission is monitored in a data processing unit. The data processing unit has a plurality of software modules, between which data is exchanged, a check sum is allocated to the data of a data transmission, which, in selected software modules is advanced by a plurality of places through one of the software modules.

Abstract: A decoding method of a product code calculates a kth soft output value of each of r C1 codewords [Ct] (t=1, 2, . . . , r) detected at a codeword generating step. Beginning from t=1, if a kth value of a C1 codeword [Ct] is zero, a first variable, with a predetermined initial value, is compared with the likelihood of the codeword. The first variable is substituted with the sum of a greater one of the first variable and the likelihood and a correction value of the difference between them. If the kth value is nonzero, then the second variable is updated in the same manner. The update of the first and second variables is carried out with incrementing t from one to r, and the kth soft output value is calculated from the difference between the first and second variables updated.

Abstract: Data packets are efficiently combined to fit into a transmission interval. A current communications condition, e.g., the current channel quality, is detected and used to select an appropriate combination of modulation and channel encoding parameters. However, data packets are combined and pre-encoded before the modulation and/or coding scheme (MCS) to be used in a specific transmission interval is known. Once the MCS is known for the transmission interval, an appropriate number of pre-processed data blocks are combined. Some complex packet processing operations can be performed in advance, without any knowledge of the MCS.

Abstract: A data coding method produces codewords with a scheme that changes for different codewords, and decodes codewords with a scheme that remains constant for all codewords. The coding method receives k user bits, codes the user bits to produce k+r output bits, corrupts any one of the output bits, and accurately reproduces at least k?r?1 user bits. Codewords coded using the appropriate initial conditions are output. For each codeword, the appropriate initial conditions are appended to the codeword coded therefrom.

Abstract: An iterative method and a device for decoding received signals transmitted in data frames via various channels. In order to be able to utilize the computing capacity of digital signal processors (DSPs) as efficiently as possible, it is proposed that, starting at a first channel, the quality of the decoded signal transmitted via the first channel is checked following every iteration and switchover takes place to at least one further channel if a specifiable switchover condition exists. The switchover condition may, for example, be a specifiable quality of the decoded signal transmitted via the channel under consideration. To determine the quality of the decoded signal a cyclic redundancy check (CRC), in particular, is proposed following every iteration.

Abstract: The error detection method includes decoding a portion of each control channel that is simultaneously received by a user equipment (UE) in a wireless communication system. The UE is provided with techniques to determine if one or more of the control channels were successfully received during the decoding step. If more than one control channel was successfully received, the method selects only one of the successfully received control channels based on calculated path metric differences (PMD) that serve as a “tie-breaking” mechanism to select the correct control channel for a particular UE.

Abstract: A method and an apparatus for recovery of particular bits in a frame are disclosed. An origination station forms a frame structure with groups of information bits of different importance. All the information bits are then protected by an outer quality metric. Additionally, the groups of more important information bits are further protected by an inner quality metric; each group having a corresponding quality metric. The frame is then transmitted to a destination station. The destination station decodes the received frame and decides, first in accordance with the outer quality metric, whether the frame has been correctly received, or whether the frame is erased. If the frame has been declared erased, the destination station attempts to recover the groups of more important information bits in accordance with the corresponding inner quality metrics.

Abstract: An Error Correcting Code (ECC) conversion facility includes a first interface for receiving input data protected in accordance with a first ECC, and first and second processing paths, each connected to the first interface. First and second decoders are incorporated into respective first and second processing paths. Each of these decoders serves to extract clear data from input data protected in accordance with the first ECC. The first processing path also includes a decoder that can protect clear data in accordance with a second ECC. The output of the system is then connected to both the first and second processing paths, and produces output data protected in accordance with the second ECC. A first portion of this output data comprises data received from the first processing path, and a second portion of the output data comprises data received from the second processing path.

Abstract: A forward error correction method for decoding coded bits generated by low density parity check matrixes. The method comprises converting each of the coded bits into a log likelihood ratio (LLR) value, and applying the converted values to variable nodes; delivering messages applied to the variable nodes to check nodes; checking a message having a minimum value among the messages, and determining a sign of the message having the minimum value; receiving messages updated in the check nodes, adding up signs of the received messages and a sign of an initial message, applying a weighting factor of 1 when all signs are identical, and when all signs are not identical, updating a message of a variable node by applying a weighting factor; determining LLR of an initial input value; and hard-deciding values of the variable nodes, performing parity check on the hard decision values, and stopping the decoding when no error occurs.

Abstract: An apparatus for testing a memory device having a plurality of data lines includes an input circuit, a compression circuit, and an output circuit. The input circuit is adapted to receive at least a first subset of the data lines and a plurality of enable signals. Each enable signal is associated with at least one of the first subset of data lines. The compression circuit is coupled to the input circuit and is adapted to detect a predetermined pattern on the first subset of data lines. The output circuit is coupled to the compression circuit and adapted to provide at least a pass signal when the predetermined pattern is detected on the first subset of data lines. The input circuit is capable of masking at least one of the first subset of data lines from the compression circuit based on the associated enable signal.

Abstract: A coding method for coding control commands for actuators includes a system that is sensitive to data transmission errors and determines a degree of danger for the system by using a system control unit. A current transmission control command is coded to form a control command code word, by using the system control device, whereby the redundancy of the control command code word depends on the determined degree of danger. The control command code word from the system control device is transmitted to an actuator control unit and decoded to form a receiving control command. The receiving control command is checked for transmission errors and at least one actuator for carrying out the receiving control command is controlled when no transmission error is detected. An actuator control unit conducts the method.

Abstract: Method for configuring a transmission chain in a 3GPP2 system for supporting a flexible or variable data rate of an information bitstream in a process for mapping an information bitstream of a data rate on a physical layer, including the steps of (1) channel coding the information bitstreams with bit rates different from each other into turbo codes or convolution codes having a value inverse of 1/coding rate, and (2) repeating coded bitstream when the channel coded bitstream is smaller than a desired interleaving size, and puncturing the coded bitstream when the channel coded bitstream is greater than the desired interleaving size, for matching the channel coded bitstream to the interleaving size.

Abstract: An apparatus for memory error control coding comprising a first circuit and a second circuit. The first circuit may be configured to generate a multi-bit digital syndrome signal in response to a read data signal and a read parity signal. The second circuit may be configured to (i) detect an error when the bits of the syndrome signal are not all the same state and (ii) generate an error location signal in response the syndrome signal. The error location signal may be generated in response to fewer than all of the bits of the syndrome signal.

Abstract: Communication decoder employing single trellis to support multiple code rates and/or multiple modulations. A single trellis is employed by the decoder to decode a plurality of encoded symbols. Each of the plurality of encoded symbols is governed by a rate control. A rate control sequence, having a period, is used to decode the plurality of encoded symbols that may be arranged within a frame. Various parameters of the plurality of encoded symbols may vary on a symbol by symbol basis; these parameters may include modulation, constellation, mapping, and/or bandwidth efficiency. For example, various symbols may be encoded differently, yet they may all be decoded using the same trellis. The functionality of this decoder may be implemented within a variety of different decoder embodiments including a trellis code modulation (TCM) decoder, a turbo trellis code modulation (TTCM) decoder, and/or a parallel concatenated turbo code modulation (PC-TCM) decoder.

Abstract: TTCM (Turbo Trellis Coded Modulation) decoder design. The design also adapts to any number of devices that perform decoding of Trellis Code Modulation (TCM) signals. After performing initial symbol processing within a data block to generate a number of check point values, the design selectively re-calculates some forward metrics (alphas) and backward metrics (betas), and the design is able to calculate extrinsic (ext) information for each symbol within the data block successively. The data block is subdivided into a number of sub-blocks that are intelligently processed to enable extremely fast processing. Generally speaking, the design performs initial processing starting from both block ends, and upon approaching the block middle, the design begins to process the block using skip backs to previous sub-blocks. The design employs a great deal of parallel and simultaneously processing to provide for very fast computation of the various values required to decode the block.

Abstract: A method and system for dynamically controlling frame retransmissions over a wireless link includes determining for a frame unsuccessfully received over a wireless link a position of the frame in a set of related frames for a packet to which the frame belongs. An allowed number of retransmissions is determined for the frame based on the position of the frame in the set of related frames. Retransmission of the frame is requested up to the allowed number of retransmissions.

Abstract: In a digital information processing system wherein a model of a finite state machine (FSM) receiving a plurality of FSM inputs and producing a plurality of FSM outputs is represented by a reduced-state trellis and wherein the FSM inputs are defined on a base closed set of symbols, a novel method is presented for updating soft decision information on the FSM inputs into higher confidence information whereby (1) the soft decision information is inputted in a first index set, (2) a forward recursion is processed on the input soft decision information based on the reduced-state trellis representation to produce forward state metrics, (3) a backward recursion is processed on the input soft decision information based on the reduced-state trellis representation to produce backward state metrics, wherein the backward recursion is independent of the forward recursion and (4) the forward state metrics and the backward state metrics are operated on to produce the higher confidence information.

Abstract: A decoder for access data stored in n memories comprises a function matrix containing addresses of the memory locations at unique coordinates. A decomposer sorts addresses from coordinate locations of first and second m×n matrices, such that each row contains no more than one address from the same memory. Positional apparatus stores entries in third and fourth m×n matrices identifying coordinates of addresses in the function matrix such that each entry in the third matrix is at coordinates that matches corresponding coordinates in the first matrix, and each entry in the fourth matrix is at coordinates that matches corresponding coordinates in the second matrix. The decoder is responsive to entries in the matrices for accessing data in parallel from the memories.