Abstract: A method and apparatus for searching for a character pattern within a data stream. A checksum is computed for one or more patterns for which the data stream will be searched. The patterns may be of the same length or they may be of different lengths. A shift register is used to sequentially parse through the data stream and compute the checksum of a series of bytes in the data stream. If the checksum of the bytes in the data stream that have been shifted into the register matches the checksum from one of the character patterns, then the character pattern corresponding to the checksum has been found. The system may search multiple character patterns simultaneously by using multiple checksum generators in parallel.

Abstract: A system and method for testing a flash memory device having uniform sectors and smaller, “boot” sectors includes determining uniform and boot test limits. The uniform and boot test limits are determined based on average erase and APDE time periods of the uniform and boot sectors, respectively. In this way, the erase test results for each sector type is compared against test limits that are based only on that sector type, thereby avoiding excessive false rejects.

Abstract: A stored data modifier modifies data starting at any arbitrary address on a storage medium that should output a data word with a multi-byte width. A masked ROM outputs a 2N-byte data word starting at an address specified as a multiple of 2N by an address signal. A correspondence detector determines whether or not correspondence is found between a correction address and one of a number 2N of addresses starting at, or preceding, the address specified by the address signal. If the correspondence detector has found the correspondence, a stored data selecting section selectively outputs, on a byte-by-byte basis, either the output of the masked ROM or correction data in accordance with the address signal and the correction address.

Abstract: An encoder adds an identifier, being different when the coding should be done or not, into a predetermined location in an original signal, while a decoder reads out the identifier added and detects the condition of coding, so as to decide the execution (ON) of the decoding process to be done or not, automatically. Further, in each of the encoder and the decoder, there is provided a delay output portion, which provides an output treated with only a specific delay but not executing the coding/decoding thereon, separately from a coding process portion or a decoding process portion, wherein a selection can be made, at which one of the signals from the respective process portions and the delay output portion should be outputted, by a setup in an outside operation system with use of a selector.

Abstract: A recording medium having a spare area for defect management and the management information of the spare area, a spare area allocation method, and a defect management method. When a primary spare area is allocated for slipping replacement and linear replacement upon initialization, and a remaining portion of the primary spare area after slipping replacement and allocated for linear replacement after initialization are insufficient, a supplementary spare area is allocated. The information on the sizes of the spare areas, and the remainder state information representing the degree of use of the spare areas, are recorded. Also, in the defect management method, when an area that has already been linearly replaced is allocated as a supplementary spare area, defective blocks within the allocated supplementary spare area are not used for linear replacement, and the entries of a secondary defect list (SDL) with respect to the defective blocks are not changed.

Abstract: System and method for improved formation of a Q-parity checkbyte matrix used for error control for a sequence of message bytes and error control bytes, using an algorithm, rather than a lookup table, to determine the order of the words used for the sequence. Entries of a Reed-Solomon parity check rectangular array are set up sequentially and diagonally, including the syndrome bytes and checkbytes to be used for error detection, so that all matrix entries can be written to, or read from, a computer memory in a stream of bytes whose order is determined by the algorithm without reference to a lookup table.

Abstract: A data transmission system for transmitting information data with a parity of an error correcting code for correcting an error in the information data. A read-out controller controls a transmitter to transmit information data and a parity so that each data component of the information data obtained by dividing the information data of one data block area into a plurality of data components and each parity component of the parity obtained by dividing the parity of one block area into a plurality of parity components are transmitted at intervals along each sector having a sector address. The sector is defined as an data area obtained by dividing one data block area of a predetermined data amount into a plurality of sectors each having an identical data amount.

Abstract: A scan flop cell and method for making the scan flop cell are provided. The scan flop cell includes a D flip-flop, a scan multiplexer, and a clock multiplexer. The clock multiplexer is configured to receive a functional clock and a scan clock. A scan mode terminal SM is connected to the scan multiplexer to control the clock output of the clock multiplexer. The scan flop cell also preferably includes a data terminal D, a scan input terminal SI, a scan enable terminal SE, a functional clock terminal C, a scan clock terminal SC, and the scan mode terminal SM. Still further, the scan flop cell can be integrated with asynchronous set and/or reset blocking circuitry, which internally converts the asynchronous set and/or reset into synchronous set and/or reset signals.

Abstract: A circuit for programmably grounding (or coupling to the positive rail) unused outputs to improve noise immunity of the circuit. The circuit of the present invention achieves, for example, programmable grounding of an output via already existing test signal paths, without introducing delays in speed critical output signal paths.

Abstract: Disclosed herein are a semiconductor integrated circuit and a recording medium wherein the amount of test data inputted from and outputted to the outside to test a plurality of circuit modules and the amount of test result data are reduced and a test time interval is shortened. When each of tested circuits is tested, test control information is externally inputted to a test interface circuit, and test control information is set to each of scan registers of circuit modules to be tested, through a test signal chain. When an instruction for a test operation is given to each of test control circuits through a control terminal, a test circuit allows the tested circuits to be tested based on the test control information on a parallel basis. Test results are read into the test interface circuit from the scan registers through the test signal chain, followed by output to the outside.

Abstract: A communication system capable of avoiding crosstalk with a simple structure. By assigning the same identification-number data to a transmitter and a receiver, performing the logical operation for the identification-number data with the logical operation circuit of the transmitter and the receiver, and detecting errors in the operation results by using error detection circuit, it is possible to perform enciphering and certifying without increasing communications traffic and thus avoid crosstalk with a simple structure because it is unnecessary to add and transmit the identification-number data.

Abstract: A method and apparatus are disclosed for testing the functionality of a queue structure. An input circuit is provided for inputting data into an input portion of the queue structure, while an output circuit is provided for retrieving data from an output portion of the queue structure. A comparison logic circuit compares the retrieved data with the input data to determine the integrity of the data that was stored in the queue structure and verify that the data from the output portion is identical to the data input to the queue. Various embodiments are disclosed for testing queue structure both in real time and in a test mode.

Abstract: Decision feedback equalizers having a stabilization capability, and methods and computer program products for stabilizing a decision feedback equalizer under severe error conditions use output samples from an equalizer to determine whether a severe error event has occurred in accordance with predefined criteria. If a severe error occurs, then a determination is made to evaluate whether the number of severe errors that have occurred has exceeded a threshold. If the threshold has been exceeded, then the coefficients for the filter(s) in the decision feedback equalizer are preserved in their current state. Severe errors can cause the equalizer filter coefficients to be pulled away from their normal operating values, which can result in several modulation cycles passing before the coefficients are restored.

Abstract: An extended symbol Galois field error correcting device is provided. The device includes a singly-extended Reed-Solomon encoder configured to generate an encoded codeword, {tilde over (c)}(x). The device also includes a channel medium that is signal coupled with the singly-extended Reed-Solomon encoder. The channel medium is configured to receive the encoded codeword, {tilde over (c)}(x), and output a received input codeword, {tilde over (r)}(x). The channel medium is capable of introducing error, {tilde over (e)}(x), to the encoded codeword, {tilde over (c)}(x). The device further includes a singly-extended Reed-Solomon decoder that is coupled with the channel medium. The singly-extended Reed-Solomon decoder is configured to receive the received input codeword, {tilde over (r)}(x). The singly-extended Reed-Solomon decoder has error detection circuitry and extended symbol correction circuitry.

Abstract: Apparatus for testing integrated circuits containing a controller or other sequential circuit at actual operating speed while minimizing the length of the test sequence and achieving high fault coverage are provided. The states of a state register are assumed controllable and observable, and a set of test patterns is obtained for a combinational circuit not containing said state register. An invalid-state generation logic circuit is added for generating invalid states, which are states contained in the generated test patterns but cannot be set by a normal transition from the reset state. A multiplexer is added for selecting the output of a next-state generation logic circuit or the invalid-state generation logic circuit for input to the state register based on a state transition mode selection signal. Signals corresponding to pseudo-primary outputs during test generation are made observable, and the multiplexer output signal is externally detectable as a state output signal.

Abstract: This invention describes a method to test both auto-refresh and self refresh of an SDRAM. The method writes a logical zero in to a single cell on each word line using a write with auto-precharge and increments an internal counter with either auto-refresh or self refresh to select the row address. The test is performed using existing circuitry on the SDRAM, and when testing self refresh, the refresh cycle is exited shortly after a cell on a row has been written into so as to not run the entire refresh cycle and save test time. A test signature is formed by the logical zeros written into one cell along each word line. Comparing this signature with the signature that should exist provides an easy way to determine if there is a test error and where the error occurred.

Abstract: A method for decoding an algebraic-coded message including determining a discrepancy indicator; determining an error locator polynomial according to a modified Berlekamp-Massey algorithm such that an uncorrectable message is detected; and producing a perceptible indication of the detected uncorrectable message. An apparatus includes storage devices, arithmetic components, and an uncorrectable message detector.

Abstract: A partitioned pseudo-random logic test (PRLT) for integrated circuit chips for improving manufacturability is disclosed. The technique makes available previously difficult-to-collect empirical data to accurately improve test effectiveness while significantly lowering test time and test cost. An embodiment includes a method for testing IC chips, including generating values for latches for a complete test pattern set, partitioning the test pattern set into a plurality of partitioned test pattern subsets, and running the subsets against a chip. Another embodiment is directed to a system that tests IC chips, having a latch value generator that generates values for latches for a complete test pattern set, a test pattern divider that partitions the complete test pattern set into a plurality of partitioned test pattern subsets, and a tester that runs the partitioned test pattern subsets against the chip.

Abstract: A method for error correction coding (ECC) by using shuffling of a digital data supplied as a bit stream in a digital-video home system. Three methods are suggested for error correction coding/decoding. One method is where an outer ECC process for 18 ECC blocks is performed earlier than an inner ECC process for the 18 ECC blocks. Another method is where an outer ECC process and an inner ECC process for an ECC block are carried out sequentially and implemented in order for 18 ECC blocks. These two methods employ a predetermined shuffling algorithm. The third method is where an outer ECC process is firstly performed for 18 ECC blocks by using the shuffling algorithm, and then an inner ECC process is implemented by the sync block according to a recording order on tracks. The outer parity information is produced by processing the data from the shuffled sync block.

Abstract: A high-speed turbo decoder utilizes a MAP decoding algorithm and includes a streamlined construction of functional units, or blocks, amenable to ASIC implementation. A gamma block provides symbol-by-symbol a posteriori state transition probability estimates. Two gamma probability function values are provided via selection switches to the alpha and beta blocks for calculating the alpha and beta probability function values, i.e., performing the alpha and beta recursions, respectively, in parallel, thus significantly increasing decoding speed. A scaling circuit monitors the values of the alpha and beta probability functions and prescribes a scale factor such that all such values at a trellis level remain within the precision limits of the system. A sigma block determines the a posteriori state transition probabilities (sigma values) and uses the sigma values to provide soft-decision outputs of the turbo decoder.