Abstract: A parity generating circuit in a 0 side receives input signals on respective signal lines and produces a parity bit based on the input signals. A parallel/serial converting circuit multiplexes parallel signals (or input signals) and the parity bit into a serial signal with reference to a timing signal. A serial/parallel converting circuit in a 1 side reproduces parallel signals and a parity signal and produces a parity check timing signal. A parity checking circuit checks a parity of the parallel signals by the use of the parity signal. If normal, a state holding circuit holds outputs of the parity checking circuit as a state signal. If abnormal, held content of the state holding circuit is cleared.

Abstract: A method of testing an electronic device including first and second semiconductor devices connected to each other with a plurality of bus lines. First, the first semiconductor device supplies a selected one of the bus lines with a first logical output signal. Then, the second semiconductor device acquires a first bus line signal from the selected bus line. The second semiconductor device inverts the first bus line signal to generate a second logical output signal. The second semiconductor device transmits the second logical output signal to the first semiconductor device. The first semiconductor device receives a second bus line signal from the selected bus line. The first semiconductor device compares the first logical output signal and the second bus line signal to detect a connection between the first semiconductor device and the second semiconductor device.

Abstract: Bit error rate or bit error probability of a received signal of a wireless telecommunication system is estimated, wherein a channel impulse response is estimated from the received signal, and the received signal is subjected to a channel equalizing operation performed on the basis of time statistics derived from the channel impulse response. Additionally, adaptive reference time domain characteristics are calculated from a weighting information obtained from the channel impulse response estimation that may be used to perform a reference channel equalizing operation for obtaining an additional output signal to be compared with the output signal of the channel equalizing operation so as to determine an estimation of the bit error rate based on the detected difference.

Abstract: A system and method are provided for non-causal channel equalization in a communications system. The method comprises: receiving a non-return to zero (NRZ) data stream input; establishing thresholds to distinguish a first bit estimate; comparing the first bit estimate in the NRZ data stream to a second bit value received prior to the first bit, and a third bit received subsequent to the first bit; in response to the comparisons, determining the value of the first bit; tracking the NRZ data stream inputs in response to sequential bit value combinations; maintaining long-term averages of the tracked NRZ data stream inputs; adjusting the thresholds in response to the long-term averages; and, offsetting the threshold adjustments to account for the asymmetric noise distribution. Two methods are used to offset the threshold adjustments to account for the asymmetric noise distribution: forward error correction (FEC) decoding and tracking the ratio of bit values.

Abstract: A memory-efficient convolutional interleaver/deinterleaver with a memory array, a write commutator, and a read commutator wherein the commutators perform their respective write and read operations relative to a preselected memory cell after a predetermined delay. The delay is chosen using a modulo-based technique, such that an efficient implementation of a Ramsey Type-II interleaver is realized.

Abstract: Presented herein are system(s), method(s), and apparatus f or detecting and recovering from false synchronization. When incorrect checksums are encountered, false synchronization and general noisy considerations are distinguished as causes of the incorrect checksums by examining the header data. For example, in one embodiment, a count can be kept and false synchronization and noisy conditions can be distinguished based on the number of detected null packets. In another embodiment, a count of detected PAT packets can be kept, and false synchronization and noisy conditions can be distinguished based on the number of detected PAT packets. In another embodiment, continuity information can be monitored and false synchronization and noisy conditions can be distinguished based on the continuity of the data packets.

Abstract: An approach is provided for transmitting messages using low density parity check (LDPC) codes. Input messages are encoded according to a structured parity check matrix that imposes restrictions on a sub-matrix of the parity check matrix to generate LDPC codes. The LDPC codes are transmitted over a radio communication system (e.g., satellite network), wherein a receiver communicating over the radio communication system is configured to iteratively decode the received LDPC codes according to a signal constellation associated with the LDPC codes. The receiver is configured to iteratively regenerating signal constellation bit metrics after one or more decoding iterations.

Abstract: Techniques are provided for the addition and comparison operations associated with a Viterbi decoding algorithm at substantially the same time. To this end, an operation of the type a±b>c±d (where a and b are to be added, c and d are to be added, and then the sums compared to determine the larger of the two sums) can be formulated, in accordance with the invention, into a±b?c?d>0 (where the addition of a and b and of c and d, and their comparison, are substantially concurrently performed). More specifically, in order to facilitate substantially concurrent addition and comparison operations in a Viterbi decoder, in one embodiment, the present invention performs multi-operand addition in a carry save form. With the results of addition represented in carry save form, the evaluation of comparator conditions is relatively straightforward.

Abstract: A C3 module in an optical storage apparatus and operation method thereof are disclosed. When the format of data to be read is audio, the C3 module enters a power saving mode. When the data format is non-audio, the C3 module enters an operation mode. The C3 module has an error correction module and an error detection module. When the error correction module is operating, the error detection module enters the power saving mode. When the operation of the error detection module is finished, the error correction module enters a power saving mode. When the error detection module is operating, the error correction module enters the power saving mode. When the operation of the error detection module is finished, the error detection module enters the power saving mode.

Abstract: An apparatus for accessing DVD data is provided. In the apparatus for accessing the data of a DVD, a row data buffer and an error detection code file are added. The row data buffer stores the row data from the row data interface, and the error detection code file records the error detection code stored in the memory. When an error occurs in the error detection code, the error detection code in the error detection code file may be modified. In addition to the normal data access, the method of accessing DVD data only re-access when a certain error occurs during RSPC decoding.

Abstract: A test-program generator capable of implementing a methodology, based on a formal language, for scheduling system-level transactions in generated test programs. A system to be tested may be composed of multiple processors, busses, bus-bridges, shared memories, etc. The scheduling methodology is based on an exploration of scheduling abilities in a hardware system and features a Hierarchical Scheduling Language for specifying transactions and their ordering. Through a grouping hierarchy, which may also be expressed in the form of an equivalent tree, the Hierarchical Scheduling Language combines the ability to stress related logical areas of the system with the possibility of applying high-level scheduling requests. A method for generating testcases based on request-files written in the Hierarchical Scheduling Language is also presented.

Abstract: A communications method carries out error-correction encoding of data, generation of a suitable packet in accordance with a retransmission request from a receiving side, and transmission of the packet to the receiving side, from a transmission side. In the receiving side, the communications method performs error-correction decoding of the received data, distinguishing an uncorrectable block in accordance with a result of the error-correction decoding, and transmission of a retransmission request packet to the transmitting side. In this way, if a block in the packet is judged as uncorrectable by the receiving side, where one packet is composed of a plurality of correction blocks of error correction codes of a block type, it is possible to retransmit only the block to be retransmitted. Therefore, it is possible to avoid unnecessary use of bands and to attain a low bit rate.

Abstract: An object of the invention is to effectively prevent erroneous transmission data from being repeatedly transmitted at the time of transmitting data. At the time of data transmission, the user designates a transmission destination from a transmission destination registration table (D1) in a storing unit (23). To achieve the object, a display control unit (313) determines whether or not error information is associated with the designated transmission destination in the transmission destination registration table (D1). If the error information is associated, an error notification is displayed on a display (12) to notify the user of the occurrence of the error and to stimulate the user to counter the error. When the data transmitting apparatus (1) receives an E-mail, an error determining unit (314) determines whether the E-mail is an error mail or not. If it is an error mail, error information is added to the transmission destination registration table (D1).

Abstract: A wafer burn-in test mode circuit includes a command decoder, an address latch circuit configured to latch an address signals, a register configured to store a wafer burn-in address signal from the address latch, a wafer burn-in test mode entry circuit configured to generate a wafer burn-in test mode entry signal according to the wafer burn-in address signal and a command signal from the command decoder, a shift registers configured to shift the wafer burn-in address signal according to the wafer burn-in test mode entry signal and a wafer burn-in clock signal, a wafer burn-in test priority decision circuit configured to output test priority signals according to output signals of the shift registers, and a decoder configured to decode the output signals of the shift registers according to the priority signals and configured to output wafer burn-in test signals corresponding to a wafer burn-in test item.

Abstract: The concurrent memory control turbo decoder solution of this invention uses a single port main memory and a simplified scratch memory. This approach uses an interleaved forward-reverse addressing which greatly relieves the amount of memory required. This approach is in marked contrast to conventional turbo decoders which employ either a dual port main memory or a single port main memory in conjunction with a complex ping-ponged scratch memory. In the system of this invention, during each cycle accomplishes one read and one write operation in the scratch memories. If a particular location in memory, has been read, then that location is free. The next write cycle can use that location to store its data. Similarly a simplified beta RAM is implemented using a unique addressing scheme which also obviates the need for a complex ping-ponged beta RAM.

Abstract: For reducing time required for error correction in an error correction device, data are transferred from a buffer memory not only to a syndrome calculator but also to an error detector at the same time, and until the syndrome calculator detects an error-containing code, the error detector performs error detection in parallel with the syndrome calculation done by the syndrome calculator. During error detection after the error corrector corrects the error, mid-term results of the error detection obtained before an error-containing code is detected are used. Consequently, it becomes unnecessary to transfer all data from the buffer memory to the error detector, thereby making execution of an error detection process possible at a halfway point.

Abstract: An apparatus and a method for filtering glitches in a data communications controller receiving asynchronous input data signals varying between two signal levels representing two bit values and having a predetermined input bit period, and sending output data signals corresponding to the input data signals. Glitches are detected in the input data signals by detecting reversals of signal level having a duration less than the input bit period. A glitch time value corresponding to the glitch duration is determined, and then a sampling clock rate is set at a rate determined from the glitch time value. The input data signals are sampled at the sampling clock rate to generate a sequence of input data samples. A voting number of input data samples are monitored and an output signal is provided, representing the value of a majority of the sequential input data samples.

Abstract: Self-test instructions are loaded from a tester into a configuration array of a memory device, and then a control circuit of the memory device sequentially reads and executes the self-test instructions while the tester is in an idle state. Data patterns are written to a main memory array of the memory device the internal self-test process. The control circuit includes a comparator for detecting defective memory cells by comparing data values read from the main array with the data pattern previously written into the main memory array. A BIN counter identifies the currently-executed self-test instruction, and is read and transmitted to the tester when an error is detected.

Abstract: A multi-user turbo decoder combining multi-user detection and forward error correction decoding is disclosed in which randomly ordered indices are assigned to interfering users before a decoding tree is constructed in the multi-user decoder for each symbol interval for every iteration and for each new block of data. By building the decoding tree in this manner for each symbol interval, a reduced complexity search is more likely to include paths (and nodes) in the tree containing the correct value for the channel symbols. All users thus share in the benefit of root level placement in the decoding tree. In an alternative embodiment of the invention only one decoding pass is accomplished and there is no re-construction of the decoding tree based on further random index ordering for iterative decoding. No modification to the transmitted signaling method is needed.

Abstract: A method for encoding a status PDU including receiving AMD PDUs, determining whether or not there are missing AMD PDUs, calculating an error-checking range and at least one error-occurrence range if it is determined that there are missing PDUs, calculating a distance ratio using the error checking range and error occurrence range, determining whether or not the distance ratio is greater than or equal to a threshold value, selecting a type of super-field for constituting a status PDU based on a determination result, encoding the status PDU with the type of selected super-field, and sending the encoded status PDU to a sending party.