Abstract: An apparatus and method for generating an initial puncturing matrix from which a first sub-code is produced in a communication system. The apparatus includes a turbo encoder for generating information symbols and first and second parity symbols for an information bit stream and a sub-code generator for generating sub-codes from the information symbols and the first and second parity symbols using puncturing matrices. The method includes the steps of selecting a number of information symbols equal to a number of columns in the initial puncturing matrix from the information symbols output from the turbo encoder, if a difference between the number Ns of selected symbols in the initial puncturing matrix and the number of the columns in the initial puncturing matrix is equal to or greater than a number of component encoders in the turbo encoder, and selecting a number of first and second parity symbols equal to the difference.

Abstract: A row redundancy system is provided for replacing faulty wordlines of a memory array having a plurality of banks. The row redundancy system includes a remote fuse bay storing at least one faulty address corresponding to a faulty wordline of the memory array; a row fuse array for storing row fuse information corresponding to at least one bank of the memory array; and a copy logic module for copying at least one faulty address stored in the remote fuse bay into the row fuse array; the copy logic module is programmed to copy the at least one faulty address into the row fuse information stored in the row fuse array corresponding to a predetermined number of banks in accordance with a selectable repair field size.

Abstract: Units of forward error correction (FEC) encoded bits each represent a one-bit data value and include correctness bits that together reflect a probability that the one-bit data value represented by the unit is correct. The units of FEC encoded bits are decoded by using the correctness bits to perform soft-decision convolution decoding on the units of FEC bits. Subsequences of units that are prone to erroneous soft-decision convolution decoding are detected by determining, whether the distribution of quality bits indicate the units are below a threshold level of correctness, and by comparing characteristics of that distribution to a given set of characteristics predetermined to be prone to result in incorrect decoding. Among the symbols produced for block decoding, symbols that correspond to units that were in detected subsequences are flagged or tagged for erasure during subsequent soft-decision block decoding.

Abstract: Disclosed is an apparatus and method for generating a QCTC (Quasi-Complementary Turbo Code) considering a characteristic of a turbo code in a packet communication system or a communication system using an ARQ (Automatic Repeat reQuest) scheme by segmenting a length N of the QCTC into a predetermined number of sections, determining SPIDs (Sub-code Packet Identifications) corresponding to the segmented sections, and specifying one of the SPIDs allocated for initial transmission of the sub-code; calculating a number of remaining symbols represented by N-Fs, where N is a length of the QCTC and Fs is a starting symbol position of the sub-code of the QCTC; determining a last symbol position Ls of the sub-code by comparing the number of the remaining symbols with a length of the sub-code; and sequentially transmitting symbols of the sub-code from the starting symbol position Fs to the last symbol position Ls.

Abstract: A QCTC (Quasi-Complementary Turbo Code) generating apparatus having: a turbo encoder for generating an information symbol sequence and a plurality of parity symbol sequences by encoding the information symbol sequence; a channel interleaver for individually interleaving the symbol sequences, generating new parity symbol sequences by multiplexing the symbols of parity symbol sequences with the same priority levels, and serially concatenating the information symbol sequence and the new parity symbol sequences; and a QCTC generator for generating a sub-code with a given code rate by recursively selecting a predetermined number of symbols from the concatenated symbol sequence at a given starting position.

Abstract: A data reproduction device in conformity to Viterbi decoding includes an inverted-selected path generation part for receiving a selected path and an inverted candidate, selecting and modifying the selected path corresponding to the inverted candidate so as to produce a inverted-selected path that is an inverted version of the selected path, and outputting a number of the inverted-selected paths in parallel, the number corresponding to a number of the inverted candidates selected for the selected path of a predetermined data length and a second candidate data generation part for generating second candidate data from the inverted candidate. The device further includes a data selection part for selecting between the first and the second candidate data based on error detecting results.

Abstract: A computer system enabling dynamic sparing employs a standby component which is identical to three other additional components and which operates like these other three active components while the computer system is running. Any one of these three other active components can be spared out dynamically in the computer system while it is running using a result of voting scheme and connecting of these four components in such a way that the system can dynamically spare while the system is still in operation. Such dynamic sparing gives the system a better reliability and availability when compared to today's computer system.

Abstract: A two-stage sampling data detector for a partial response channel having a channel code encoder for encoding user information sequences into blocks of code words in accordance with a predetermined channel block code characterized by a list of most likely error-events comprising impermissible code words. The detector includes a first-stage detector, such as a Viterbi detector, connected to receive samples from the partial response channel and matched to characteristics of the channel and not to the channel code, puts out unchecked bit estimates. A second stage post-processor checks the bit estimates in relation to derived detector decision metrics information and the channel block code, and puts out post-processed bit estimates to a channel code decoder after correcting detected erroneous sequences in accordance with the decision metrics information, information derived from the channel code, and the list of most likely error-events. A method for generating the channel block code is also described.

Abstract: Techniques for performing substantially concurrent add-compare-select-add operations and substantially concurrent compare-select-add operations for use in turbo decoders are provided. In one aspect of the invention, a technique for processing data in accordance with a turbo decoder comprises the following steps. Data values of two sets of input data are respectively added to generate a set of sums. Substantially concurrent with the addition step, correction values are respectively added to the sums to generate a set of corrected sums. Substantially concurrent with the respective input data value and correction value addition steps, the sums are compared against one another, and an absolute value of a difference between the sums is compared against base and bound values. Then, one of the corrected sums is selected based on the comparison steps. Preferably, respective sub-steps within the input value addition step, the correction value addition step, and the comparison step are performed concurrently.

Abstract: A semiconductor integrated circuit device includes a test target circuit, a control circuit, and an observation circuit. The control circuit generates a reset signal, and an operation mode signal. The observation circuit is controlled by the signals, and receives input data from observation points in the test target circuit. The observation circuit includes a plurality of flip-flops. The observation circuit performs a reset operation in response to the reset signal. The observation circuit selectively performs a signature-compression operation, and a serial operation of outputting the test result, in response to the operation mode signal. The signature-compression operation is performed, using input data generated in the test target circuit in accordance with test patterns for a normal functional operation.

Abstract: A method and apparatus for reclaiming bus bandwidth on a full duplex bus. A source node sends a primary packet toward a destination node along a full duplex bus. If the destination node identifies an inability to accept the primary packet, it sends a NAK in the opposite direction along the full duplex bus towards the source node. Upon receiving the NAK, the source node aborts packet transmission of the primary packet which by virtue of the NAK has been identified as futile. Accordingly, the bandwidth, which would have otherwise have been used for the futile packet transmission, can be reclaimed and used for some other purpose.

Abstract: A recording medium having a spare area for defect management and the management information of the spare area, a spare area allocation method, and a defect management method. When a primary spare area is allocated for slipping replacement and linear replacement upon initialization, and a remaining portion of the primary spare area after slipping replacement and allocated for linear replacement after initialization are insufficient, a supplementary spare area is allocated.

Abstract: A system and method are provided for non-causal channel equalization in a communications system. The method comprises: establishing a first threshold (V1) to distinguish a high probability “1” first bit estimate; establishing a second threshold (V0) to distinguish a high probability “0” first bit estimate; establishing a third threshold (Vopt) to distinguish first bit estimates between the first and second thresholds; receiving a non-return to zero (NRZ) data stream; comparing the first bit estimate in the data stream to a second bit value received prior to the first bit; comparing the first bit estimate to a third bit value received subsequent to the first bit; in response to the comparisons, determining the value of the first bit.

Abstract: A random access memory (RAM) device for use in a high-speed pipelined Reed-Solomon decoder, a method of accessing the memory device, and a Reed-Solomon decoder having the memory device are provided. The memory device, which data is written to and read from at the same time during decoding of one frame of data, includes a random access memory (RAM) having a plurality of banks; and a control circuit for setting a first bank pointer, which selects a first bank among the plurality of banks, and a second bank pointer which selects a second bank among the plurality of banks, wherein the first and second bank pointers are set to banks with a predetermined offset every frame of data.

Abstract: A method and apparatus for allocating CRC (Cyclic Redundancy Check) codes in a flash ROM (Read-Only Memory). The apparatus includes a flash ROM and a microprocessor. The flash ROM is logically divided into a plurality of data blocks. Each data block contains a CRC code block that includes a plurality of bytes for saving CRC codes. The microprocessor can write to and read from the flash ROM, calculate a complement code of a sum of all the bytes of the data block, and add the complement code to data of one of the plurality of bytes. The microprocessor thus generates new CRC codes and writes them to the corresponding CRC code block. The new CRC codes generated can meet the critical requirement of CRC. That is, the sum of all the bytes of the data block (including the CRC code block) is null.

Abstract: A decoder that receives, as input, probability information AMP/CR×yt. This probability information is obtained by dividing a channel value obtained by multiplication of received value yt and a predetermined coefficient AMP by the first additive coefficient CR for regulating the amplitude of the received value yt and the probability information 1/CA×APPt obtained by multiplying the a priori probability information APPt by the reciprocal of the second additive coefficient CA for regulating the amplitude of the a priori probability information APPt to a soft-output decoding circuit. The soft-output decoding circuit, which may be a large scale intergrated circuit, generates log soft-output CI×I?t and/or external information 1/CA×EXt using additive coefficients for regulating the amplitude of arithmetic operations in the inside of the soft-output decoding circuit.

Abstract: According to the invention, a JTAG-compliant chip having a controller that receives data provided on the TDI input pin and forms parallel address and data instructions and passes the data through IO pins to the non-JTAG chip is able to verify whether the data was correctly received by the non-JTAG chip by reading back the data and comparing to the original data. A status bit or bits are shifted out on a TDO pin and used to determine what data will be shifted in next.

Abstract: A system and method that calculates multiple bytes of data in a single cycle. The invention uses at least two CRC circuits to calculate a CRC value for a string of data. A first CRC circuit is used for calculating multiple bytes at a time. A second CRC circuit is used for calculating a single byte. The first CRC circuit is only used when there are multiple bytes to be processed. If there are other CRC circuits, then data is directed to the appropriate CRC circuit, i.e., the CRC circuit that calculates the appropriate number of bytes, when the number of bytes remaining to be processed is less than the first CRC circuit can process. Otherwise, the data is directed to the second CRC circuit, and must be processed one byte at a time until there is no more data remaining.

Abstract: A wireless communications device is disclosed, in which certain digital coding functions are realized according to a modified multiplier architecture. The device includes an encode and modulate function within which convolutional coding function is provided. The convolutional coding function may be realized as a modified parallel multiplier, in which carries among adder units are ignored or not generated. The datastream is applied to the multiplier as the multiplicand, while successive sets of code generator polynomial coefficients are applied as a multiplier. Carry-in and carry-out bits among the adder units are blocked in a coding mode, but passed in a multiplier mode. A similar arrangement of a modified parallel multiplier circuit may be used in generating a scrambling code that is applied prior to transmission.

Abstract: An error detector at a receiver comprises a feedback shift register. A shift direction in the feedback shift register is opposite to a shift direction at a transmitter in generating a transmission bit string by using a specified generator polynomial. A reception bit string is inputted to the feedback shift register in reverse order to the transmission bit string was generated at the transmitter so that errors in the reception bit string is detected by obtaining the remainder. Another error detector at a receiver comprises first and second feedback shift registers. Respective shift directions in the first and second feedback shift registers are the same as and opposite to a shift direction at a transmitter in generating a transmission bit string.