Abstract: In a semiconductor memory capable of verifying data stored therein, a verification pass signal output from a verification circuit is input to a control signal output circuit. In the case of a normal mode operation of the control signal output circuit, a signal having a voltage level corresponding to that of the verification pass signal is output therefrom. In the case of a test mode operation of the control signal output circuit, a signal having a given voltage level regardless of voltage level of the verification pass signal is output therefrom. In cases where the signal having the given voltage level is output from the control signal output circuit, a write control circuit and a write counter execute a preset maximum number of program processings and verifications processing.

Abstract: A method and apparatus are provided for checksum verification with receive packet processing for communications over a data communications network. First a data communications connection is identified. Responsive to an identified data communications connection, a start of data packet is identified. Then a header checksum is calculated. A protocol checksum including a protocol pseudo header and data is calculated. An embedded processor structure is used for tracking packet state and running CRC calculations across received packets, and performing full checksum verification.

Abstract: A computer system is disclosed which includes at least one microprocessor having an L2 cache, at least one memory, and basic input output system (BIOS) firmware. The L2 cache includes error checking and correcting capability (ECC). The at least one memory includes either all ECC capable memory or any combination of ECC capable and non-ECC capable memory. Lastly, the basic input output system (BIOS) firmware includes an L2 cache support feature. The L2 cache support feature includes three user-selectable options, the three options including i) L2 cache ECC ON, ii) L2 cache ECC OFF, and iii) L2 cache AUTO. Selection of L2 cache ECC ON is for enabling L2 cache ECC. Selection of L2 cache ECC OFF is for not enabling L2 cache ECC. Lastly, selection of L2 cache ECC AUTO is for automatically enabling or not enabling L2 cache ECC in response to a detection of the presence of a) all ECC capable memory or b) any combination of ECC and non-ECC capable memory, respectively.