Abstract: A more accurate charge pump reduces phase error in a PLL. An UP input pulse causes a p-channel drive transistor to charge a filter capacitor on the output, while a down DN input pulse causes an n-channel drive transistor to discharge the output. The drive transistors are connected to power or ground through a supply transistor. The supply transistor is biased on in the linear region and is not switched off. The sources of the drive transistors are always driven by the supply transistors, preventing phase error from floating sources. The drive transistors are common-gate switches with their gates biased by a compensating bias generator. The p-channel drive transistor current variations with Vds are compensated by providing a similar current variation to the n-channel drive transistor. Thus the bias is adjusted to compensate for drain-source voltage changes that can cause the up and down currents from the drive transistors to mismatch.

Abstract: A method and an apparatus for biasing a charge pump in a phase locked loop in a circuit and generally for biasing a circuit through the use of a replica circuit. The method and apparatus make use of a replica circuit including substantially similar circuit elements to those circuit elements making up the circuit to be biased. Through the use of comparison and bias techniques, the replica circuit and the circuit to be biased are both biased. The bias conditions result from a comparison of the operation of the replica circuit and the circuit to be biased. Since the replica circuit operates in a manner substantially similar to an expected operation mode of the circuit to be biased, the bias conditions resulting from the comparisons will cause the circuit to be biased to operate similarly to how the replica circuit operates, while still handling external influences such as loading.

Abstract: A plurality of output transistors for an output buffer of a semiconductor device are provided in parallel. Potentials to be applied to gates of output transistors are set to different levels upon conduction of the output transistors. By sequentially rendering the transistors conductive in the order of increasing voltage during conduction, rapid flow of a large amount of current is prevented, thereby reducing ringing. More preferably, the transistors are increased in size according to the order of conduction of the output transistors.

Abstract: An improved semiconductor integrated circuit and power supply wiring designing method and system is described in which the wiring resources have been effectively used without oppressing the same. The semiconductor integrated circuit in accordance with the present invention comprising: a semiconductor chip; an integrated circuit formed within the semiconductor chip; a first power supply pad; a first power supply wiring having a cyclic pattern formed on the integrated circuit for the purpose of supplying power to the integrated circuit from the first the power supply pad; a second power supply pad; and a second power supply wiring having an acyclic pattern formed on the integrated circuit for the purpose of supplying supplementary power to the integrated circuit from the second power supply pad.

Abstract: A digital frequency-doubling circuit includes a pair of cascaded first delay circuits, each including a plurality of cascaded delays, and a first stage of the cascaded first delay circuits receiving an input signal to be frequency-doubled, and an exclusive-OR circuit receiving the input signal and a delayed output signal outputted from the first stage of the cascaded first delay circuits, for generating a frequency-doubled signal. A delay amount comparator receives a first delayed output signal outputted from a second stage of the cascaded first delay circuits and a second delayed output signal outputted from a second delay circuit of a small delay receiving the first delayed output signal, for performing comparison at a transition timing of the input signal, to discriminate whether the obtained frequency-doubled signal advances or delays in comparison of an optimum duty ratio.

Abstract: A comparator (20, 30) for comparing first and second current inputs includes a first stage that has a first resistor (43) being coupled to a first input node and operable to produce the a first voltage level corresponding to the first current input at a first voltage node when a CLK signal is high. A second resistor (45) is provided and is coupled to a second input node and operable to produce a second voltage level corresponding to the second current input at a second voltage node when the CLK signal is high. A pair of cross-coupled transistors (36, 37) are coupled to the first and second voltage nodes when a CLK signal is high and are operable to latch the first and second voltage levels when the CLK signal is high. A first differential amplifier (60) is coupled to the first voltage node and is operable to receive the latched first voltage level at a non-inverting input and the latched second voltage level at an inverting, input and to generate a first amplified voltage level when the CLK signal is high.

Abstract: A timing circuit can be selectively configured to generate output pulses in response to either the falling edges or the rising edges of an input signal. The timing circuit includes a multiplexer, an output pulse width controller (OPWC), a gating circuit (GC) and a latch circuit. The OPWC includes a delay circuit that can be configured to provide a predetermined delay .delta. that can be larger than the pulse width of the input signal pulses. The multiplexer is connected to receive a first input signal and an inverted version of a second input signal. The first input signal is used in a rising edge triggered mode, whereas the second input signal is used in a falling edge triggered mode. The multiplexer receives a mode signal to selectively output one of the input signals to the GC. The GC is also connected to receive the output signal from the OPWC.

Abstract: An internal power supply circuit for use in a semiconductor device includes a clamp circuit for clamping an internal voltage to a constant level. The clamped internal voltage is distributed to internal circuits of the semiconductor device through an output node. When the internal voltage rises momentarily due to noise in the internal power supply circuit due to open-circuit phenomenon, the rising internal voltage is discharged through the clamp circuit, thereby maintaining the internal voltage at a constant value. The clamp circuit includes a first transistor for discharging the output node, and a diode-connected transistor for generating a charge voltage at the gate of the first transistor. The threshold voltage of the diode-connected transistor is preferably equal to or lower than the threshold voltage of the first transistor.

Abstract: An improved charge pump circuit includes one switch element driven by a ramp waveform to precisely control the output voltage. The circuit includes a switch group having one or more switch elements for transferring a charge to one or more capacitors, a feedback circuit having an error amplifier for amplifying a difference between a divided output voltage and a reference voltage, a compensation circuit for phase compensating the feedback network, an oscillator for generating the ramp waveform, and a control circuit for driving the one or more switch elements. At least one of the switch elements has a resistance that can be adjusted externally and is driven by the ramp waveform such that its resistance varies with time. Accordingly, the charge transferred from a power source to the one or more capacitors can easily be adjusted. When the charge transferred is small, the on-time of the ramp waveform is short and the average value of the resistance is large.

Abstract: A charge pump circuit comprises a plurality of booster stages. Each booster stage has a first node, a second node, a first charge pump and a second charge pump. Both charge pumps operate in a complementary manner, and raise potential of the second node relative to potential of the first node by transferring charge from the first node to the second node. Each charge pump comprises a pumping capacitor, an NMOS transistor and a PMOS transistor. In each charge pump, the NMOS transistor is used for charging the pumping capacitor with charge input through the first node, and the PMOS transistor is used for discharging the pumping capacitor to send charge to the second node.

Abstract: It is possible to reduce the voltage drop on sub-power supply lines for reducing the subthreshold current and thereby prevent the operating speed of a logic circuit from lowering. Main power supply lines are arranged along one side of a rectangular region including a MOS logic circuit whose subthreshold current must be reduced, and a plurality of sub-power supply lines are arranged on the region in the direction perpendicular to the main power supply lines. A plurality of switching MOS transistors for selectively electrically connecting the sub-power supply lines to the main power supply line are dispersedly arranged with respect to the main power supply line. By dispersedly arranging the switching MOS transistors with respect to the main power supply line, it is possible to reduce the equivalent resistance of the sub-power supply lines compared to the case where switching MOS transistors are provided at one place.

Abstract: A differential circuit used in an input interface of a memory device comprises a current mirror including a pair of P-channel transistors, a differential pair including a pair of N-channel transistors for receiving a reference voltage and an input signal voltage, respectively, and another N-channel transistor connected between the common sources of the pair of N-channel transistors and GND line. The another N-channel transistor has a gate maintained at a constant potential irrespective of the fluctuations of the source voltage, thereby suppressing a current increase due to variations of the source voltage and reference voltage. The constant voltage is generated in the memory device itself and used for another purpose.

Abstract: An apparatus for turning power to a device on and off is disclosed. The apparatus comprises a first signal input, a second signal input, a first charge output electrically connected with the first signal input, a transistor electrically connected with the second signal input, and a second charge output electrically connected with the transistor. The first charge output, when the first signal input and second signal input are powered on, electrically ramps up a first portion of the device. This ramp up of the first portion draws from current available to ramp up a second portion of the device. The second charge output is, thus, provided. The second charge output, when the first signal input and second signal input are powered on, electrically charges the transistor and the transistor electrically ramps up the second portion of the device concurrently with the ramp up of the first portion.

Abstract: A current source circuit includes a series-circuit connected between a power source node and ground and comprising a reference current source circuit, a first transistor Q1 of an NPN type having its collector and base connected to each other and a second transistor Q2 having a multi-emitter area (N) and having a multi-emitter configuration. The current source circuit further includes a third transistor Q3 of an NPN type connected at its collector to the power source node, at its base to the base of the first transistor Q1 and at its emitter connected to the base of the second transistor and has an emitter area (M) and an input current source circuit connected between the emitter of the third transistor Q3 and ground to allow a flow of an input current Iin.

Abstract: A frequency-independent voltage divider includes a series arrangement of resistors connected between an input terminal and a reference terminal for receiving an input signal. An output terminal for supplying an output signal is coupled to a tap of the series arrangement. The influence of parasitic capacitances is eliminated by compensation capacitors.

Abstract: A redundant circuit for a semiconductor device including a fuse program means producing a control signal determining whether or not a chip is normal; a high-voltage generating means producing a first voltage or second voltage according to a control signal from the fuse program means; and an on-chip redundant decoding means driven by the first voltage or second voltage produced from the high-voltage generating means. In case that the chip is normal, the high-voltage generating means generates the first voltage, and in case that the chip fails, the high-voltage generating means produces the second voltage. The first voltage is an output voltage from the high-voltage generating means, and the second voltage is an output voltage higher than the first voltage.

Abstract: Integrated buffer circuits include an output driver powered at a first power supply voltage (EVC) and a voltage boosting circuit which drives an input (DOK) of the output driver and is powered at a second power supply voltage (VINTQ) having a magnitude less than a magnitude of the first power supply voltage. An internal power supply voltage generator is provided which generates the second power supply voltage at a level which varies inversely with increases in the first power supply voltage in order to minimize timing skew associated with the output driver. This is achieved by lowering the voltage of the signal applied to the input (DOK) of the output driver to compensate for the output driver being powered at an increased first power supply voltage.

Abstract: In one embodiment of the invention, a semiconductor circuit includes a first group of field effect transistors that are forward body biased and have threshold voltages and a second group of field effect transistors that are not forward body biased and have threshold voltages that are higher than the threshold voltages of the first group of field transistors. In another embodiment of the invention, a semiconductor circuit includes first and second groups of field effect transistors. The circuit includes voltage source circuitry to provide voltage signals to bodies of the first group of field effect transistors to forward body bias the transistors of the first group. When the voltage signals are applied, the transistors of the first group have lower threshold voltages than do the transistors of the second group, except that there may be unintentional variations in threshold voltages due to parameter variations.

Abstract: The present invention includes a first switch 4a, a second switch 4b and a capacitor 4d. The first switch 4a normally in a closed state is connected in series between a power source 1 and load, and opens when an accident builds up. The second switch 4b normally in an open state closes almost simultaneously with the opening of the first switch 4a. The capacity 4d normally charged by an arbitrary voltage has predetermined electrically capacity. The serial connected circuit consists of the second switch 4b and capacitor 4d, it is connected in parallel to the first switch 4a.

Abstract: A validity circuit is used with an analog circuit in a mixed signal system to determine whether the supply voltage is at an adequate voltage level to assure stable operation of the analog circuit. The validity circuit generates a "valid" signal that is used to activate the mixed signal system when the voltage level of the supply voltage is adequate. Where the voltage level of the supply voltage is inadequate to produce a stable output signal from the analog circuit, the analog circuit will stop generating a valid signal indicating that any output signal generated by the analog signal is unstable. The logic circuit is thus deactivated to avoid producing inaccurate or unreliable results. Where the analog circuit is a bandgap voltage reference circuit, the validity circuit is connected to two nodes within the feedback loop of the bandgap voltage reference circuit.