Patents Examined by Keith Christianson
  • Patent number: 6281032
    Abstract: In a semiconductor device manufacturing method capable of manufacturing semiconductor lasers, light emitting diodes or electron transport devices using nitride III-V compound semiconductors with a high productivity, a GaN semiconductor laser wafer is prepared in which a plurality of semiconductor lasers are formed on an AlGaInN semiconductor layer on a c-face sapphire substrate and separated from each other by grooves deep enough to reach the c-face sapphire substrate, and a p-side electrode and an n-side electrode are formed in each semiconductor laser. The GaN semiconductor laser wafer is bonded to a photo-diode built-in Si wafer having formed a photo diode for monitoring light outputs and solder electrodes in each pellet by positioning the p-side electrode and the n-side electrode in alignment with the solder electrodes, respectively.
    Type: Grant
    Filed: April 14, 1999
    Date of Patent: August 28, 2001
    Assignee: Sony Corporation
    Inventors: Osamu Matsuda, Toshimasa Kobayashi, Norikazu Nakayama, Hiroji Kawai
  • Patent number: 6281099
    Abstract: In growing single AlN thin films on a semiconductor substrate by rapidly cooling a beam of atomic Al and atomic or molecular N obtained by exciting or decomposing N2 with an electromagnetic wave on the semiconductor substrate, an n-type dopant and a p-type dopant in the form of atomic beams are simultaneously doped in a crystal, so that pairs of an n-type dopant and a p-type dopant are formed in the crystal to synthesize single crystal AlN thin films of low resistivity n-type and low resistivity p-type.
    Type: Grant
    Filed: March 6, 2000
    Date of Patent: August 28, 2001
    Assignee: Japan Science and Technology Corporation
    Inventor: Hiroshi Yoshida
  • Patent number: 6277714
    Abstract: The method of the invention induces crystallization in an amorphous semiconductor layer, and includes the steps of: a) producing a patterned metal layer on a first substrate, the metal layer exhibiting a weak level of adherence to the first substrate; b) pressing the metal layer into physical contact with the amorphous semiconductor layer; c) applying heat, light or both to the metal layer and amorphous semiconductor layer to cause a reaction therebetween and a crystallization of the amorphous semiconductor that is juxtaposed to the metal.
    Type: Grant
    Filed: September 21, 1999
    Date of Patent: August 21, 2001
    Assignee: The Penn State Research Foundation
    Inventors: Stephan J. Fonash, Sanghoon Bae
  • Patent number: 6277668
    Abstract: An optical detector is provided including a substantially annular metallic ring positioned on either side of an active (i.e. intrinsic) region of the optical detector to minimize optical crosstalk. Optical crosstalk originates from adjacent optical sources (e.g., VCSELs) emitting light toward the direction of the optical detector. The metallic ring prevents the light which propagates substantially parallel to a base of the optical detector from reaching the active region of the optical detector.
    Type: Grant
    Filed: January 4, 2000
    Date of Patent: August 21, 2001
    Assignee: Lucent Technologies, Inc.
    Inventors: Keith W. Goossen, Ashok V. Krishnamoorthy
  • Patent number: 6277715
    Abstract: Provided is a production method for a silicon epitaxial wafer having an internal gettering (IG) capability at a level equal to that of a CZ silicon mirror-finished wafer. In the production method for a silicon epitaxial wafer in which silicon single crystal is epitaxially grown on a silicon wafer; a heat treatment of the silicon wafer is performed at a temperature within ±50° C. of a holding temperature for the first stage heat treatment which is to be firstly effected as a heat treatment in the device fabrication process after the epitaxial growth process for a time period equal to or more than a time period in which a precipitate nucleus from interstitial oxygen in the silicon wafer can grow to a size which survives through the epitaxial growth process, prior to the epitaxial growth process, and thereafter, the epitaxial growth is effected; or a heat treatment of the silicon wafer is performed being kept at a temperature within ±50° C.
    Type: Grant
    Filed: May 28, 1999
    Date of Patent: August 21, 2001
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Hiroshi Takeno, Yoshinori Hayamizu
  • Patent number: 6274463
    Abstract: A method for crystallizing an amorphous film formed on an underlying layer having an unfavorable crystalline growth morphology is disclosed. The method includes providing a favorable growth substrate and then forming a first unfavorable growth layer on a seeding surface of the favorable growth substrate. An aperture is etched in the first unfavorable growth layer so that the aperture extends through the first unfavorable growth layer down to the seeding surface thereby exposing a portion of the seeding surface. An amorphous media layer is then formed on the first unfavorable growth layer. The amorphous media layer fills the aperture and is in contact with the seeding surface of the favorable growth substrate.
    Type: Grant
    Filed: July 31, 2000
    Date of Patent: August 14, 2001
    Assignee: Hewlett-Packard Company
    Inventor: Alison Chaiken
  • Patent number: 6274398
    Abstract: The present invention relates to a method for manufacturing a plurality of semiconductor photonic integrated circuit comprising at least a laser and a modulator connected optically to one another. Each laser and modulator has a waveguide layer being implemented on a single substrate, where said modulator is formed by use of a selective area growth technique. By providing modulator masking parts with selectable width to compensate a difference in band-gap energy in the waveguide layer between the laser and the modulator a approximate uniform difference in band-gap energy between the optically connected laser and modulator may be obtained.
    Type: Grant
    Filed: December 17, 1999
    Date of Patent: August 14, 2001
    Assignee: Telefonaktiebolaget LM Ericsson (publ)
    Inventors: Eskil Bendz, Lennart Lundqvist
  • Patent number: 6271104
    Abstract: The subject invention involves a method of preparing defect-free semiconductor material layers by growing a semiconductor material buffer layer on a substrate, masking with a dielectric film, and etching to open spaced seed windows. Another layer of a III-V or II-VI material is then grown in the longitudinal direction from the seed window, followed by lateral growth of the same material to form an epitaxial film and a structure which provides a defect free surface for further epitaxial layers.
    Type: Grant
    Filed: August 6, 1999
    Date of Patent: August 7, 2001
    Assignee: MP Technologies
    Inventors: Manijeh Razeghi, Patrick Kung
  • Patent number: 6270587
    Abstract: The present invention provides an epitaxial wafer comprising a (111) substrate of a semiconductor having cubic crystal structure, a first GaN layer having a thickness of 60 nanometers or more, a second GaN layer having a thickness of 0.1 &mgr;m or more and a method for preparing it.
    Type: Grant
    Filed: March 12, 1998
    Date of Patent: August 7, 2001
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Kensaku Motoki, Masato Matsushima, Katsushi Akita, Mitsuru Shimazu, Kikurou Takemoto, Hisashi Seki, Akinori Koukitu
  • Patent number: 6271061
    Abstract: A semiconductor power device comprising an insulated gate bipolar transistor, of the type which comprises a semiconductor substrate with a first type of conductivity and an overlying epitaxial layer with a second type of conductivity, opposite from the first, and whose junction to the substrate forms the base/emitter junction of the bipolar transistor, has the junction formed by a layer of semiconductor material with conductivity of the second type but a higher concentration of dopant than that of the epitaxial layer. Furthermore, the device has the epitaxial layer with conductivity of the second type provided with at least two zones at different dopant concentrations, namely a first lower zone being part of the junction and having a higher dopant concentration, and a second upper zone having a lower concentration.
    Type: Grant
    Filed: July 16, 1999
    Date of Patent: August 7, 2001
    Assignee: STMicroelectronics S.r.l.
    Inventors: Ferruccio Frisina, Leonardo Fragapane
  • Patent number: 6268235
    Abstract: In a method of manufacturing a photoelectric conversion device, a step of forming a microcrystalline semiconductor film and a step of implanting an impurity element into the microcrystalline semiconductor film are separated from each other so that the productivity of the photoelectric conversion device by a roll-to-roll system manufacturing apparatus is increased. In the method, first, a first electrode is formed on an organic resin substrate. Then a first microcrystalline semiconductor film, a substantially intrinsic amorphous semiconductor film, and a second microcrystalline semiconductor film are continuously formed by a roll-to-roll system plasma CVD method. The first and second microcrystalline semiconductor films are formed without adding n-type or p-type conductivity determining impurity elements. After the formation of the films, a p-type conductivity determining impurity element is implanted into the second microcrystalline semiconductor film.
    Type: Grant
    Filed: January 21, 1999
    Date of Patent: July 31, 2001
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Masayuki Sakakura, Yasuyuki Arai, Shunpei Yamazaki
  • Patent number: 6265241
    Abstract: The present invention relates to a method of forming a photo diode on a semiconductor wafer. The method comprises forming a pad silicon oxide layer on the substrate and a silicon nitride layer on the pad silicon oxide layer. Then, remove portion of the silicon nitride layer over which the remaining silicon nitride layer defines a photo sensor area and at least one dummy active area on the pad silicon oxide layer. Next, each dummy active area are positioned surrounding the photo sensor area with a narrow slot in between which is not covered by the silicon nitride layer. Next, perform a thermal oxidation process over the slot to form a field oxide layer, the dummy active area is used to reduce the thickness of the field oxide layer in the slot. Then, remove the remaining silicon nitride layer by using a wet etching process.
    Type: Grant
    Filed: October 22, 1999
    Date of Patent: July 24, 2001
    Assignee: United Microelectronics Corp.
    Inventor: Jui-Hsiang Pan
  • Patent number: 6265287
    Abstract: The method for producing a semiconductor of the present invention grows a compound semiconductor on a substrate held by a susceptor provided in a reaction chamber in accordance with a metalorganic vapor phase epitaxy technique. The method includes the steps of: supplying a Group III source gas containing indium and a Group V source gas containing nitrogen into the reaction chamber; and mixing the Group III and Group V source gases, supplied into the reaction chamber, with each other, and supplying a rare gas as a carrier gas into the reaction chamber so as to carry the mixed source gas onto the upper surface of the substrate.
    Type: Grant
    Filed: October 28, 1998
    Date of Patent: July 24, 2001
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Ayumu Tsujimura, Yoshiaki Hasegawa, Akihiko Ishibashi, Isao Kidoguchi, Yuzaburo Ban
  • Patent number: 6265289
    Abstract: A sidewall of an underlying gallium nitride layer is laterally grown into a trench in the underlying gallium nitride layer, to thereby form a lateral gallium nitride semiconductor layer. Microelectronic devices may then be formed in the lateral gallium nitride layer. Dislocation defects do not significantly propagate laterally from the sidewall into the trench in the underlying gallium nitride layer, so that the lateral gallium nitride semiconductor layer is relatively defect free. Moreover, the sidewall growth may be accomplished without the need to mask portions of the underlying gallium nitride layer during growth of the lateral gallium nitride layer. The defect density of the lateral gallium nitride semiconductor layer may be further decreased by growing a second gallium nitride semiconductor layer from the lateral gallium nitride layer. In one embodiment, the lateral gallium nitride layer is masked with a mask that includes an array of openings therein.
    Type: Grant
    Filed: June 7, 1999
    Date of Patent: July 24, 2001
    Assignee: North Carolina State University
    Inventors: Tsvetanka Zheleva, Darren B. Thomson, Scott A. Smith, Kevin J. Linthicum, Thomas Gehrke, Robert F. Davis
  • Patent number: 6265237
    Abstract: A method of manufacturing and testing a laser device that facilitates in-wafer testing of the laser device includes forming the laser device on a wafer and forming a light detecting device on the wafer adjacent to the laser device. The laser device should include a grating. The method further includes causing the laser device to lase while in the wafer and detecting light generated from the laser device with the light detecting device. Finally, the method includes obtaining an electro-optic parameter of the laser device from the detected light.
    Type: Grant
    Filed: December 15, 1999
    Date of Patent: July 24, 2001
    Assignee: Lucent Technologies Inc.
    Inventors: William Rudolph Heffner, John E. Johnson
  • Patent number: 6261857
    Abstract: A process for fabricating a waveguide with a desired tapered profile is disclosed. The waveguide has a first section with a first height and a second section with a second height. The first height is greater than the second height. The waveguide height tapers from the first height to the second height. The waveguide is a compound semiconductor material and is formed using selective area growth. In selective area growth, a dielectric mask is formed on a substrate. The dimensions of the dielectric mask are selected to provide a waveguide with the desired dimensions. The compound semiconductor material is deposited on the substrate using chemical vapor deposition. The dielectric mask affects the rate at which the compound material is deposited in areas of the substrate proximate to the mask. Therefore, the profile of the waveguide formed using the selected mask dimensions is modeled and compared with the desired profile.
    Type: Grant
    Filed: June 17, 1998
    Date of Patent: July 17, 2001
    Assignee: Agere Systems Optoelectronics Guardian Corp.
    Inventors: Muhammad Ashrafal Alam, Mark S. Hybertsen, Roosevelt People
  • Patent number: 6261860
    Abstract: There is provided a method of fabricating a solid-state image sensor, comprising the step of carrying out heat treatment before formation of a gate of the solid-state image sensor, a maximum temperature in the heat treatment being in the range of 1000 to 1200 degrees centigrade both inclusive, the step of carrying out heat treatment further including the steps of (a) carrying out lamp-up at least twice, and (b) carrying out lamp-down at least twice. The method makes it possible to grow BMD (Bulk-Micro-Defect) in a wafer in a greater size than a size of BMD to be grown in accordance with a conventional method, ensuring reduction in illuminated or white defect.
    Type: Grant
    Filed: March 30, 1999
    Date of Patent: July 17, 2001
    Assignee: NEC Corporation
    Inventor: Tsuyoshi Nagata
  • Patent number: 6258633
    Abstract: A method for producing an interconnect from a first metal trace, through a dielectric, to a second metal trace. The method comprises the steps of heating a portion of the first metal trace to cause thermal expansion and at least partial melting thereof and heating a portion of the second metal trace to cause thermal expansion and at least partial melting thereof such that the thermal expansion of the traces causes at least one crack or fissure in the dielectric to be formed between the traces and such that the melting of the traces causes the metals to fuse together through the crack or fissure, thereby producing the interconnect from the first metal trace to the second metal trace. One of the metal traces may comprise a substantially square donut shape configuration having four interior edges portions, wherein the probability of a successful interconnection is increased due to the increased number of edges present on the top layer from which a crack or fissure to the lower layer can form.
    Type: Grant
    Filed: July 7, 1997
    Date of Patent: July 10, 2001
    Assignee: University of South Florida
    Inventors: Rex Alan Lee, Wilfrido Alejandro Moreno
  • Patent number: 6258619
    Abstract: A semiconductor light emitting device includes a substrate, an n-type layer formed of gallium-nitride based compound semiconductor formed on the substrate, and a p-type layer formed of gallium-nitride based compound semiconductor formed on the substrate. Semiconductor overlying layers are constituted by the n-type layer and the p-type layer on the substrate. A light emitting layer is formed together with the n-type and p-type layers in the semiconductor overlying layers to emit light. At least one of the n-type layer and the p-type layer is formed by three or more overlying sublayers including a sublayer of AlyGa1-yN (0<y≦0.5) and a sublayer of AluGa1-uN (0≦u<y). With this structure, the semiconductor light emitting device is almost free from lattice mismatch to thereby enhance electron mobility and hence light emission efficiency even where the overlying semiconductor layers are different in lattice constant from the substrate.
    Type: Grant
    Filed: June 22, 1999
    Date of Patent: July 10, 2001
    Assignee: Rohm LTD
    Inventors: Masayuki Sonobe, Shunji Nakata, Yukio Shakuda, Tsuyoshi Tsutsui, Norikazu Itoh
  • Patent number: 6248600
    Abstract: Post-manufacturing analysis of a semiconductor device is enhanced via a method that uses a light emitting diode (LED) formed in a semiconductor die. According to an example embodiment of the present invention, a LED is formed within a semiconductor die having a circuit side opposite a back side. The LED is activated and generates radiation. Substrate is removed from the device, and the amount of radiation that passes through the substrate is detected. The amount of radiation that passes through the die is a function of the absorption characteristics of the die and the substrate thickness. By detecting the radiation and using the absorption characteristics of the die, the amount of substrate remaining in the back side of the die is determined and the substrate removal process is controlled therefrom.
    Type: Grant
    Filed: September 30, 1999
    Date of Patent: June 19, 2001
    Assignee: Advanced Micro Devices
    Inventors: Michael R. Bruce, Jeffrey D. Birdsley, Rosalinda M. Ring, Rama R. Goruganthu, Brennan V. Davis