Patents Examined by Keith Christianson
  • Structure of critical dimension bar
    Patent number: 6350994
    Abstract: A structure of a critical dimension bar. The critical dimension bar is formed on a substrate between the dies. A base layer is formed on a portion of the substrate, and a critical material layer is formed on the die, the base layer and the substrate with a uniform thickness. The base layer has a thickness to result in a surface profile the same as the die. A die photomask pattern, a first and a second test photomask patterns on a photomask are then transferred to the critical material on dies, the base layer and the substrate, respectively. These three photomask patterns have the same pattern width.
    Type: Grant
    Filed: November 17, 2000
    Date of Patent: February 26, 2002
    Assignee: United Microelectronics Corp.
    Inventors: Kun-Yuan Chang, Chia-Ming Cheng
  • Method for determining metal concentration in a field area
    Patent number: 6348701
    Abstract: The concentration of metal atoms in a field area between two trench structures is determined by applying a voltage on one of the trench structures and grounding the other. The resultant current flow between the trench structures is measured and used as an indicator of metal concentration in the field area.
    Type: Grant
    Filed: October 19, 1999
    Date of Patent: February 19, 2002
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Young-Chang Joo, Amit P. Marathe
  • Method for producing semiconductor laser module
    Patent number: 6348360
    Abstract: A method for producing a semiconductor laser module is provided which enables simplifying the production process by eliminating the process of positioning the laser light emitting portion on the substrate, as well as enabling positioning an optical fiber on an appropriate position without aligning the optical fiber with the laser light emitting portion. A semiconductor laser module is fabricated through a process including a substrate preparation step for preparing a substrate including an active layer between cladding layers; a supporting groove portion formation step for forming a supporting groove portion to support an optical fiber on the substrate; and an electrode formation step for forming an electrode on a substrate surface of an opposing portion which faces the supporting groove portion.
    Type: Grant
    Filed: March 17, 2000
    Date of Patent: February 19, 2002
    Assignee: Pioneer Corporation
    Inventors: Nong Chen, Kiyoshi Takei, Yoshiaki Watanabe, Kiyofumi Chikuma
  • Semiconductor sensor structure and method of manufacturing the same
    Patent number: 6346735
    Abstract: A semiconductor device includes a deformable sensor structure spaced apart from a substrate, and convexities are formed on the lower surface of the sensor structure with tips of the convexities pointing to the substrate. The convexities of the deformable sensor structure facilitate reducing the contact area between the sensor structure and the substrate and attractive force caused by surface tension of an etchant or washing liquid. Thus, the structure prevents the sticking phenomena, improves the throughput and reduces the manufacturing costs.
    Type: Grant
    Filed: August 29, 2000
    Date of Patent: February 12, 2002
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Katsumichi Ueyanagi, Mitsuo Sasaki
  • Quantum dot infrared detection device and method for fabricating the same
    Patent number: 6346431
    Abstract: Quantum dot infrared detection device and method for fabricating the same, which is a new concept of detection device in which quantum dots in the quantum dot part having a stack of alternative quantum dots and separating layers are doped with impurities, so that the quantum dot part itself absorbs infrared ray and serves as a channel for transferring electrons generated by the infrared ray absorption, for enhancing device performance and a device uniformity, and simplifying a device structure and a device fabrication process.
    Type: Grant
    Filed: July 10, 2000
    Date of Patent: February 12, 2002
    Assignee: LG Electronics Inc.
    Inventors: Tae Kyung Yoo, Jae Eung Oh
  • Method of fabricating a diffraction grating
    Patent number: 6344367
    Abstract: A first resist layer (21) and a second resist layer (22) are formed on a base material (11) in the recited order, the first resist layer (21) being removable by etching and the second resist layer (22) being a photosensitive resist layer in which either exposed or unexposed regions become soluble in a developing solvent upon emission of light. Near-field light is then emitted to the second resist layer (22) by means (24) for emitting near-field light (27) according to a diffraction grating pattern upon reception of the light. Next, the diffraction grating pattern is formed in the second resist layer (22) by developing the second resist layer (22). The first resist layer (21) is etched with the pattern in the second resist layer (22) as an etching mask, and a diffraction grating pattern consisting of the first and second resist layers (21, 22) is formed.
    Type: Grant
    Filed: July 10, 2000
    Date of Patent: February 5, 2002
    Assignee: Fuji Photo Film Co., Ltd.
    Inventors: Masayuki Naya, Toshiaki Fukunaga
  • Light emitting diode array and method of forming the same
    Patent number: 6342402
    Abstract: A light emitting diode array includes a light emitting area formed on a semiconductor substrate, a diffusion prevention layer formed on the semiconductor substrate, and an insulating layer formed on the diffusion prevention layer. The diffusion prevention layer has a lower edge and the insulating layer has a level drop at this lower edge. An interconnection conductor extends on the insulating layer and is in ohmic contact with the light emitting region through holes in the insulating layer and the diffusion prevention layer. The interconnection conductor has a stepped portion at the level drop of the insulating layer, the stepped portion being located in a wide-width segment of the interconnection conductor.
    Type: Grant
    Filed: December 13, 1999
    Date of Patent: January 29, 2002
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Tomoyoshi Tajiri, Takao Kusano, Kazuya Ohkawa
  • Methods for fabricating distributed reflection multi-layer film mirrors
    Patent number: 6337222
    Abstract: In a method for fabricating distributed reflection multi-layered film mirrors consisting of a plurality of laminated thin films having a different refractive index, the thin films are formed using a liquid phase film formation method. The liquid phase film formation method includes a step of applying thin film materials forming the thin films, and a step of drying the applied the thin film materials. The liquid phase film formation method utilizes an ink jet method. Thin films can be formed in fine patterns with ease and in a short amount of time. Laminated layers with high reliability can be obtained in very fine patterns. The reflection properties such as film thickness and reflectance of distributed reflection multi-layered film mirrors can be controlled with ease.
    Type: Grant
    Filed: October 14, 1999
    Date of Patent: January 8, 2002
    Assignee: Seiko Epson Corporation
    Inventors: Tatsuya Shimoda, Takeo Kaneko, Satoru Miyashita
  • Method of fabricating a semiconductor light-emitting element
    Patent number: 6335212
    Abstract: A device and a method for fabricating said device provides a semiconductor light-emitting element having an electrode and a protective film layer that is sealed with an insulating resin, which is hardened at high temperature. After completion of the hardening process, the semiconductor light-emitting element is heat treated in an atmosphere of normal or higher humidity. Preferably, the heat treatment is performed at a temperature of 60° C. or higher in an atmosphere having an absolute humidity of 10 KPa or higher. When the heat treatment is performed at or above 10 KPa, the heat treatment can be completed within a shorter timeframe in comparison to such a device heat treated at an absolute humidity of less than 10 kPa.
    Type: Grant
    Filed: June 23, 2000
    Date of Patent: January 1, 2002
    Assignee: Toyoda Gosei Co., Ltd.
    Inventors: Toshiya Uemura, Takahide Oshio
  • GaN type semiconductor device fabrication
    Patent number: 6335217
    Abstract: A GaN type semiconductor layer having a structure is provided which incorporates a substrate having surface which is opposite to a GaN type semiconductor layer and which is made of Ti.
    Type: Grant
    Filed: March 14, 2000
    Date of Patent: January 1, 2002
    Assignee: Toyoda Gosei Co., Ltd.
    Inventors: Toshiaki Chiyo, Shizuyo Noiri, Naoki Shibata, Jun Ito
  • Method for fabricating a group III nitride semiconductor device
    Patent number: 6335218
    Abstract: A group III nitride semiconductor device producing method is constructed by: a step of forming a first crystal layer made of a group III nitride semiconductor (AlxGa1−x)1−y.InyN (0≦×≦1, 0≦y≦1) doped with a group II impurity element; a step of a second crystal layer made of a group III nitride semiconductor AlzGa1−zN (0.7≦z≦1) onto the first crystal layer; and a step of removing at least a part of the second crystal layer by etching after the formation of the first and second crystal layers.
    Type: Grant
    Filed: May 5, 2000
    Date of Patent: January 1, 2002
    Assignee: Pioneer Corporation
    Inventors: Hiroyuki Ota, Mamoru Miyachi, Yoshinori Kimura
  • Semiconductor substrate and method for producing the same
    Patent number: 6335269
    Abstract: The present invention provides a semiconductor substrate comprising a non-porous monocrystalline layer with decreased crystal defects which is formed on a porous silicon layer, and a method of producing the substrate. The method of producing the substrate comprises a heat treatment step of heat-treating a porous layer in an atmosphere not containing a silicon type gas, and a step of growing a non-porous monocrystalline silicon layer on the porous silicon layer, wherein the heat treatment step is executed such that the etched thickness of silicon is 2 nm or less and that the rate of change r for the Haze value of the porous silicon layer defined by (the Haze value after the heat treatment)/(the Haze value before the heat treatment) satisfies the relationship between 1≦r≦3.5.
    Type: Grant
    Filed: September 3, 1999
    Date of Patent: January 1, 2002
    Assignee: Canon Kabushiki Kaisha
    Inventor: Nobuhiko Sato
  • Memory of multilevel quantum dot structure and method for fabricating the same
    Patent number: 6333214
    Abstract: A semiconductor memory having a multilevel quantum dot structure is formed by alternatively disposing conductive layers and insulation layers, and processing these layers so that quantum dots are formed in the conductive layers. The writing and reading of data into the semiconductor memory are achieved by using the principle of Coulomb blockade and quantized voltage drops. The size and distribution of the quantum dots are controlled by agglomeration, selective oxidation, etc. in order to achieve the desired quantum dot layer structure so that the immigration of charges between a semiconductor channel and each quantum dot layer is different.
    Type: Grant
    Filed: June 17, 1999
    Date of Patent: December 25, 2001
    Assignee: Hynix Semiconductor Inc.
    Inventors: Ki Bum Kim, Tae Sik Yoon, Jang Yeon Kwon
  • Integrated photo sensor
    Patent number: 6333544
    Abstract: A sensor portion of an integrated photo sensor is composed of a silicon substrate, a photo diode and a signal processing element which are provided on the silicon substrate separately from each other. A shading film is provided on a surface region of the substrate except a region above the photo diode, and an intermediate insulating film made of silicon oxide is provided between the silicon substrate and the shading film. The intermediate insulating film includes a part extending on a light-receiving region of the photo diode, and the part is covered with light transmittable gel having a refractive index approximately equal to that of the intermediate insulating film.
    Type: Grant
    Filed: July 26, 2000
    Date of Patent: December 25, 2001
    Assignee: Denso Corporation
    Inventors: Inao Toyoda, Yoshitaka Gotoh
  • Method for introducing dopants into semiconductor devices using a germanium oxide sacrificial layer
    Patent number: 6333245
    Abstract: A method for introducing dopants into a semiconductor device using doped germanium oxide is disclosed. The method includes using rapid thermal anneal (RTA) or furnace anneal to diffuse dopants into a substrate from a doped germanium oxide sacrificial layer on the semiconductor substrate. After annealing to diffuse the dopants into the substrate, the germanium oxide sacrificial layers is removed using water thereby avoiding removal of silicon dioxide (SiO2) in the gates or in standard device isolation structures, that may lead to device failure. N+ and p+ sources and drains can be formed in appropriate wells in a semiconductor substrate, using a singular anneal and without the need to define more than one region of the first doped sacrificial layer. Alternatively, annealing before introducing a second dopant into the germanium oxide sacrificial layer give slower diffusing ions such as arsenic a head start.
    Type: Grant
    Filed: December 21, 1999
    Date of Patent: December 25, 2001
    Assignee: International Business Machines Corporation
    Inventors: Toshiharu Furukawa, Mark C. Hakey, Steven J. Holmes, David V. Horak, William H. Ma, Donald W. Rakowski
  • Defect compensation method for semiconductor element
    Patent number: 6331474
    Abstract: A defect compensation method for a semiconductor element to compensate for defects of the semiconductor element, in which hot water is conducted with the semiconductor element to accomplish defect compensation. On the basis of this treatment, excessive progress of oxidation of the crystal grain boundary and retention of water and OH− groups in the film are provented.
    Type: Grant
    Filed: August 1, 2000
    Date of Patent: December 18, 2001
    Assignee: Canon Kabushiki Kaisha
    Inventors: Ryo Hayashi, Keishi Saito
  • Method of fabrication of semiconducting compounds of nitrides A3B5 of P-and N-type electric conductivity
    Patent number: 6329215
    Abstract: The subject of the Invention is the method of fabrication of nitride semiconductor A3B5 such as GaN, AlN, InN or their solid solutions, characterized by p- or n-type conductivity, high intensity of emitted light and high structural quality. The semiconductors obtained by this method are applied in the construction of light emitting devices, light detectors and electric current amplifiers such as for example: highly efficient blue and green light diodes, laser diodes and high power lasers, ultraviolet detectors and high temperature field transistors.
    Type: Grant
    Filed: December 6, 1999
    Date of Patent: December 11, 2001
    Assignee: Centrum Badan Wysokocisnieniowych Polskiej Akademii Navk
    Inventors: Sylwester Porowski, Jan Jun, Tadeusz Suski, Czeslaw Skierbiszewski, Michal Leszczynski, Izabella Grzegory, Henryk Teisseyre, Jacek Baranowski, Elzbieta Litwin-Staszewska
  • Semiconductor cleaning method
    Patent number: 6329268
    Abstract: In a method of manufacturing a semiconductor device that has an amorphous-silicon film onto which hemispherical grains are grown, a silicon wafer is cleaned at an elevated temperature using amnmonia hydrogen peroxide water solution, cleaned at an elevated temperature using chlorine hydrogen peroxide water solution, and then immersed in dilute hydrofluoric acid solution, after which it is rinsed with pure water, after which the amorphous-silicon film surface of the wafer is dried using isopropyl alcohol.
    Type: Grant
    Filed: November 25, 1998
    Date of Patent: December 11, 2001
    Assignee: NEC Corporation
    Inventors: Masaharu Nakamori, Ichiro Honma
  • Two-dimensionally arrayed quantum device fabrication method
    Patent number: 6319738
    Abstract: A quantum device is constituted from a two-dimensional array of quantum dots formed from metal atom aggregates contained in a metalloprotein complex. The metalloprotein is arranged on the surface of a substrate having an insulation layer with a pitch of the size of the metalloprotein complex. The diameter of the metal atom aggregates used in the quantum device is 7 nm or smaller, and the pitch of the metalloprotein complex is preferably from 11 to 14 nm.
    Type: Grant
    Filed: May 24, 2000
    Date of Patent: November 20, 2001
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Ichiro Yamashita
  • Method of forming nitride based semiconductor layer
    Patent number: 6319742
    Abstract: A GaN layer is grown on a sapphire substrate, an SiO2 film is formed on the GaN layer, and a GaN semiconductor layer including an MQW active layer is then grown on the GaN layer and the SiO2 film using epitaxial lateral overgrowth. The GaN based semiconductor layer is removed by etching except in a region on the SiO2 film, and a p electrode is then formed on the top surface of the GaN based semiconductor layer on the SiO2 film, to join the p electrode on the GaN based semiconductor layer to an ohmic electrode on a GaAs substrate. An n electrode is formed on the top surface of the GaN based semiconductor layer.
    Type: Grant
    Filed: July 27, 1999
    Date of Patent: November 20, 2001
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Nobuhiko Hayashi, Takashi Kano