Abstract: An emulator is comprised of a host processor, an emulator, assist unit, and a memory which are closely coupled together over a co-processor bus. Stored in the memory is a user program which is a sequence of instructions from a user instruction set that is to be emulated, and a control program which is a mixture of host processor instructions and emulator assist unit instructions. In operation, the host processor reads and executes the hosts instructions, and it reads and passes the emulator assist unit instructions to the emulator assist unit for execution in that unit. By this means, the host processor and the emulator assist unit share the emulation tasks; and those tasks which are most difficult for the host are performed by the emulation assist unit.

Abstract: An access priority control system for a main storage for a computer, for controlling a signal transmission to the main storage upon receiving a plurality of storage access requests from at least one processor related to the main storage. The system includes a first access request port unit for holding at least temporarily a segment address of the storage access requests from the processor; a first control unit responsive to the output of the first access request port unit for checking bus conflict conditions and prohibition conditions for a destination storage segment determined by the address of the storage access request; a second access request port unit responsive to the output of the first control unit for holding at least temporarily an intra-segment address of the storage access request; and a second control unit responsive to the output of the second access request port unit for checking logical storage busy conditions in the storage segments.

Abstract: An interface circuit permits a first bus master connected to a first bus to directly access a main memory connected to a second bus while maintaining coherency between corresponding data in the main memory and a cache memory used by a second bus master on the second bus. The interface circuit maps selected first bus addresses to corresponding second bus addresses such that when a bus master on the first bus attempts to read or write access one of the mapped first bus addresses, the bus interface circuit responds by read or write accessing a corresponding address in the memory on the second bus.

Abstract: In this data processing device, a request for direct memory-access operation is detected as an interrupt signal. When such an interrupt is detected, a interrupt controller generates a vector corresponding to the interrupt sigal. On the basis of this vector, a DMA controller generates a control signal showing whether the interrupt signal is a normal interrupt or an interrupt for requesting the direct memory-access operation. A CPU includes a ROM for storing micro-code for achieving the direct memory-access operation. When the DMA controller generates a control signal corresponding to the interrupt signal, the CPU sequentially reads out the micro-codes, to execute the direct memory-access operation. Specifically, if an interrupt for requesting the direct memory-access operation is detected, different processing space from that used for a normal interrupt processing is accessed.

Abstract: The present invention concerns a method for manufacturing a buried stripe semiconductor laser comprising the steps of depositing by epitaxy at least the heterostructure (51, 52, 53, 54) comprising at least one active material layer (53) on a substrate (50) and then depositing a dielectric mask (55) over the structure thus obtained and etching the latter through the mask (55) to obtain stripes in the active material layer (53) and any layer or layers (54) previously deposited by epitaxy over the active material layer (53), then carrying out impurity ionic implantation in the structure, protecting the active material stripes (53) and any layer or layers (54) that may have been deposited over this material by means of a mask (55) that is not transparent to ionic implantation.

Abstract: The invention relates to a Josephson device and a method of manufacturing such a device which comprises two layers 11, 11' of an oxidic superconducting material between which at least one non-superconducting layer 13 of silver sulphate is provided. The non-superconducting layer 13 is connected to the superconducting layers 11, 11' through silver layers 12, 12'.

Abstract: A semiconductor laser assembly is provided with a photodetector module and a laser module mounted on orthogonal surfaces of a heatsink. The photodetector module includes a photodetector and two electrically isolated wire bond blocks, each with two surfaces parallel to the orthogonal surfaces of the heatsink. The laser module includes a laser diode bonded and a wire bond region with two surfaces also parallel to the orthogonal surfaces of the heatsink. Both of the wire bond block surfaces of the photodetector modules are thus parallel to the wire bond region surfaces on the laser module, allowing wire connections to be made between parallel surfaces before the heat sink is mounted on a header. One of the surfaces of each of the wire bond blocks and regions is parallel to the pins of a header, allowing attachment of wires from the photodetector module and the laser module to the pins without rotating the header and pins.

Abstract: Disclosed herein is a semiconductor laser device capable of exhibiting very low threshold current and operating in a fundamental transverse mode stably even at a high power operation, and a method for fabricating the same. The fabricating method includes only two crystal growth steps to thereby produce the semiconductor laser device capable of operating in the fundamental transverse mode at high power operation. The thus obtained device has high reproducability due to the simple fabricating process.