Abstract: A pipelined processing unit which includes an instruction unit stage containing logic management apparatus for processing a set of complex instructions. The logic management apparatus includes state control circuits which produce a series or sequence of control states used in tracking the different types of instructions of the complex instruction set being processed. Different ones of the states are used for different types of instructions so as to enable the different pipeline stages to operate both independently and jointly to complete the execution of different instructions of the complex instruction set.

Abstract: A system and method of down loading, over a network, operating systems or other executable programs to a computer which does not have a boot device or other device containing the executable program. Down loading is accomplished without modification of the loadable image. The computer has a network interface which requests a minimum-boot program be transferred from a host computer on the network. The minimum-boot program, when executed, establishes a logical connection to a disk server on the network and allows the requesting computer to treat the disk server as a local boot device.

Abstract: The functions of two virtual operating systems (e.g., S/370 VM, VSE or IX370 and S/88 OS) are merged into one physical system. Partner pairs of S/88 processors run the S/88 OS and handle the fault tolerant and single system image aspects of the system. One or more partner pairs of S/370 processors are coupled to corresponding S/88 processors directly and through the S/88 bus. Each S/370 processor is allocated from 1 to 16 megabytes of contiguous storage from the S/88 main storage. Each S/370 virtual operating system thinks its memory allocation starts at address 0, and it manages its memory through normal S/370 dynamic memory allocation and paging techniques. The S/370 is limit checked to prevent the S/370 from accessing S/88 memory space. The S/88 Operating System is the master over all system hardware and I/O devices.

Abstract: A sort accelerator is disclosed which uses a rebound sorter as a merger in which large numbers of records can be efficiently and rapidly sorted. The rebound sorter not only can sort a number of records but can be used to merge together previously sorted groups of records into larger sorted groups. A certain number of processing elements and record storage elements are used to simultaneously compare records. Depending on the sort chosen either a descending or ascending sort can be made.The merging operation consists of an input phase, and a merge-up phase, an output phase, and a final merge phase. Successively larger strings of records are created until a final sorted string of records remains. Through various enhancements and associated circuitry the rebound sorter can sort and merge large numbers of records quickly and efficiently.

Abstract: A control unit for processing modules of an integrated circuit for data processing includes at least one control module which is formed by a control operator and a gating means which exchanges input/output semaphores with upstream and downstream control modules and/or with processing modules. Each control operator, controlled by its gating means, receives microinstructions from an upstream control module and supplies microinstructions to one or more downstream control modules and/or microcommands to a downstream processing module. The control operator may comprise either a sequencer and a memory or a programmable logic array. The exchanges being controlled by the semaphores, each control module incorporates self-clocking sequencing. The control unit enables a modular design for the integrated circuit for data processing.

Abstract: A super-scaler processor is disclosed wherein branch-prediction information is provided within an instruction cache memory. Each instruction cache block stored in the instruction cache memory includes branch-prediction information fields in addition to instruction fields, which indicate the address of the instruction block's successor and information indicating the location of a branch instruction within the instruction block. Thus, the next cache block can be easily fetched without waiting on a decoder or execution unit to indicate the proper fetch action to be taken for correctly predicted branching.

Abstract: A method of handling a fault associated with a first floating point instruction upon reaching the next sequential floating point instruction is described. The first floating point instruction is decoded. A first floating point microinstruction received from a control memory is stored in a first latching means and in a second latching means. The next sequential floating point instruction is decoded. There is a jump to a plurality of exception handler microinstructions stored in the control memory, the jump occurring upon the detection of the fault associated with first floating point instruction. The plurality of exception handler microinstructions include an exception handler floating point microinstruction. The exception handler floating point microinstruction received from the control memory is stored in the first latching means, replacing the previous microinstruction stored in the first latching means.

Abstract: Method for generating a program for numerically solving a partial differential equation, wherein when a numerical calculation program for calculating, in a specified analytic domain, the value of a physical quantity defined by a partial differential equation is automatically produced, it is judged on the basis of predetermined conditions whether or not discretization due to the divergence of an operand is to be carried out for each of terms which are included in the partial differential equation and have a differential operator, and the discretization due to the divergence of the operand is carried out for a term when it is judged that the term is to be discretized on the basis of the divergence of the operand.

Abstract: An address translation apparatus is provided which has an address translation look-aside buffer with an entry composed of a real address field, virtual machine identifier field and space identifier field. For the translation look-aside buffer entry to be used by a general virtual machine which uses a plurality of address spaces, a virtual machine identifier for discrimination of a general virtual machine is stored in the virtual machine identifier field, and information used in discriminating an address space is stored in the space identifier field. For the translation look-aside buffer entry to be used by a dynamic address translation off (DATOFF virtual) machine which uses a single address space, an identifier commonly assigned to a group of DATOFF virtual machines is stored in the virtual machine identifier field, and a control block address used in discriminating a DATOFF virtual machine is stored in the space identifier field.

Abstract: A data processing system including a circuit for storing a sequence of instructions, a circuit for determining if the instruction sequence includes a branch instruction, a circuit for storing a sequence of branch target instructions in response to the determination of the existence of a branch instruction in the stored sequence of instructions, a circuit for dispatching instructions in sequence after the branch instruction to a processor to be executed on condition that a branch is to be taken before a determination of whether said branch will be taken and simultaneously for determining if the branch is to be taken, any circuit for directing the processor to execute the instructions in sequence after the branch if the branch is not taken, or, if the branch is to be taken, for dispatching the branch target instruction sequence to the processor for execution.

Abstract: A method and system for allowing an interrupted computer program to detect the occurrence of an interrupt. In a preferred embodiment, a system according to the present invention allows an Intel 80286-compatible based computer program executing in real mode to detect the occurrence of an interrupt during the execution of a set of instructions. According to a preferred method of the present invention, the LOADALL instruction is used to load the code segment selector with the segment address of the code in the interrupted routine to be executed upon return from an interrupt and to load the code segment base address with the segment base address of the set of instruction during whose execution interrupt is to be detected. A preferred method then executes the set of instructions. Upon occurrence of an interrrupt, the preferred method saves the value in the code segment selector and executes an interrupt routine.

Abstract: A processor for use in a digital data processing system includes a data path which, in the execution of a program instruction, processes generally a series microinstructions from a control circuit. In some cases, the operation to be performed by the data path depends on the results of a previous operation. The data path includes a circuit which generates preset operation codes and a multiplexer which, during those cases, enables either the microinstructions from the control circuit or the preset operation code depending on the results of the previous operation.

Abstract: A personal computer (PC) desktop workstation using a first operating system is enhanced with a single PC bus extension card (SCAMP Board) within its base housing which connects a second computer system (A-Series) having a large memory, control logic and a 2-inch.times.2-inch IC chip module holding a CPU and control store. The first operating system is organized to act as the I/O and peripheral subsystem for the second computer system so that peripheral connectivity, operational and maintenance interfaces can function with a PC keyboard, screen and peripheral devices. The workstation base housing has a footprint of less than three square feet and six inches height while providing memory and processing ability comparable to mainframe computers which are normally several volumes larger in size.

Abstract: A data processor for speedier processing of input data includes a data processing system for executing a text editing process and a text printing process by the time slice method and a preference control unit for selecting between the above processes. When data is entered into the processor, the entering process or text editing process is generally preferred to the text printing process. Therefore, no delay occurs in inputting data through a keyboard from data entry to its display. If desired, it is possible to prefer the text printing process to the text editing process.

Abstract: An interactive system for the transmission of media presentations has an interchassis communications system capable of quickly transmitting large amounts of data between its components. High efficiency of transmission is achieved by providing an industry standard interface for various types of chassis and processors forming the system. The processors and their interfaces used to transmit data within the system are interconnected so as to allow completion of the transmission of data between any two points within the system by no more than three hops between chassis.

Abstract: To execute variable-length instructions independently of instruction preprocessing, a central processing unit is provided with a set of queues in the data and control paths between an instruction unit and an execution unit. The queues include a "fork" queue, a source queue, a destination queue, and a program counter queue. The fork queue contains an entry of control information for each instruction processed by the instruction unit. This control information corresponds to the opcode for the instruction, and preferably it is a microcode "fork" address at which a microcode execution unit begins execution to execute the instruction. The source queue specifies the source operands for the instruction. Preferably the source queue stores source pointers and the operands themselves are included in a separate "source list" in the case of operands fetched from memory or immediate data from the instruction stream, or are the contents of a set of general purpose registers in the execution unit.

Abstract: A circuit for generating a synchronized flush signal for use with a cache controller which samples the noncachable address input too late for that input to be used to disable the cache controller is described. The circuit synchronizes a memory-mapped register bit with the internal clock signal in the cache controller to insure setup and hold times and proper phasing. The use of the synchronized flush signal overcomes coherency problems with the noncachable input.

Abstract: A buffer-storage control system used in a pipeline data processor includes a memory system having a two-level hierarchical structure composed of a main storage and a buffer storage having tag portion and a data portion, each portion being composed of a plurality of partitions. In the buffer-storage control system, the tag portion and the data portion can be independently accessed and the data portion is so constituted for every partition that it is possible to select one of a plurality of address passes and to select an address for a read access and an address for a write access for every partition, thereby simultaneously effecting a read operation and write operation in the same machine cycle and executing the read access again only when the read access and the write access are effected for the same partition.

Abstract: This invention relates to a method of distributing documents have a directed relationship within an information processing system. The documents in the directed relationship have a one-to-one relationship. An end user indicates to the system an identification of at least one document in the directed relationship which is to be distributed to one or more recipient end user. The end user also enters system addresses of the recipient end users. The system then builds the necessary structures to transmit the document in the directed relationship to the identified recipient end users such that the directed relationship is maintained.

Abstract: Establishing a language specific linkage between high-level graphics application programs written in a specific programming language and different intermediate-level graphics processors permit a graphics application program to be transported between and used in different graphics processing systems. A single, portable graphics application program can be used with any of the graphics processors with which an application language linkage has been established to produce graphs on an output device.