Abstract: A RICS microprocessor architecture is provided with a plurality of data registers and instruction registers each having a multi-bit extension for extending the width of the data and instruction words processed therethrough. A first plurality of bits within a tag field of the multi-bit extension are reserved for identifying the data type of the data words while a second plurality of bits provide instruction dependent control. The multi-bit extension allows full precision computation for the data words requiring the tag field to identify the data type thereof while retaining full precision compatibility for data words not needing tag field identifiers. At least two bits of the first plurality of bits in tag field are reserved for identifying one of several primary categories of data types and at least two bits identify one of several subtype categories within each of the plurality of primary categories.

Abstract: A request is issued in response to an instruction to a memory buffer control unit in accordance with one of first and second specific access methods. The request comprises a request code and a memory address. The first specific access method comprises the steps of holding preliminarily the request code in a register, producing the memory address by using an address syllable included in the instruction, and delivering the memory address and the request code held in the register to the memory buffer control unit.

Abstract: A control apparatus for a computer is described that includes an arbiter circuit for selecting a first controller for supplying the memory of the computer with a first plurality of addresses from a first bus at a first rate and for selecting the second controller for supplying the memory of the computer with a second plurality of addresses from a second bus at a second rate. The first and second controllers are selected such that the first and second controllers do not supply the memory with more than one memory address at a time. A method for controlling the use of a computer bus is also described. A plurality of requests to use the bus are received. A length of a first period for use of the bus and a length of a second period for use of the bus are preselected. Each of the plurality of requests are granted.

Abstract: A parallel processing system including a virtual processing instruction and address generator, for generating processor cell instructions to a parallel processing array such as a multi-dimensional processor array which may have fewer processor cells than the number of nodes in the problem space. The system partitions the memory of each physical processor cell into several equal sections, each section being associated with one node of the problem space. The instruction generator then produces a sequence of processor cell instructions for each node of the given problem space, with appropriate address modifications for each sequence of instructions provided by an address relocation circuit.

Abstract: Interface ciruitry for accomplishing a block transfer of information over a NuBus protocol bus having associated therewith a plurality of individual computer modules through the steps of testing to determine whether an addressed module is capable of accomplishing a NuBus protocol block transfer, conducting such a transfer if that module is capable of accomplishing a NuBus protocol block transfer, locking the bus if that module is not capable of accomplishing a NuBus protocol block transfer, conducting a series of individual data transfer operations during the period the bus is locked, terminating the individual operations, and unlocking the bus.

Abstract: An interface device for changing the serial data format of the video signal output of a computer intended for display on a cathode ray tube, to a video signal having parallel data format for a liquid crystal display is provided. The device includes a read/write control circuit which responds to a clock signal corresponding to the synchronizing signal of the serial signal and to an asynchronous clock signal. Data signals which were removed from the serial signal and temporarily stored in memory are read out as parallel data signals at the next read cycle when read address counter is counted.

Abstract: A system suitable for use on a computer network provides a user interface on a local node and an application to be run on a remote node. An application for accepting input from the user and translating it to appropriate commands for the remote application is divided, and located partially on the local node and partially on the remote node. That portion located on the local node gathers any information required from the user and transmits it to the portion located on the remote node in an efficient manner. The remote location portion uses the transmitted information to interface with the remote application and obtain results. The results are collected and transmitted to the local portion, from which they are returned to the user.

Abstract: A rank cell array for ranking a series of sample values including a number of identical rank cells (RC1, RC2. . . ) permitting ready modification of the sorting window size in an OS CFAR radar application, for example. Each rank cell (RC1, RC2. . . ) includes a multiplexer (49), a D flip-flop (41), first and second comparators (43, 45), and a multiplexer controller (49). Each clock interval, the foregoing circuitry examines the sample value entering the sorting window, the sample value leaving the sorting window, the sample value in the preceding rank cell, and the sample value in the succeeding rank cell to determine the sample value in the rank cell during the next clock interval.

Abstract: A circuit for sorting a plurality of inputted (reference-axis) data includes an index generator for generating an index (datum number) for each of the inputted data; a first buffer memory having storage areas each of which can be addressed by the data, the first buffer memory for storing an index generated by the index generator when the corresponding data is initially inputted into the index generator; a last buffer memory having storage areas each of which can be addressed by the data, the last buffer memory for updating and storing an index generated by the index generator at each time when the corresponding data is inputted thereinto; a chain buffer memory having chain index storage areas each of which can be addressed by the previous index in the chain; a first control for writing a new updated index into a chain index storage area addressed by a before-updated index at each time when the index of the last buffer memory is updated; a second control for writing the index of the data into the chain datum n

Abstract: The disclosure pertains chiefly to an interface including an electrical supply. The disclosure concerns an interface capable of providing an external supply from the amplification of one of the signals. For example, the amplified DTR is used to give a supply voltage to a MIDI interface from an RS 232 serial interface using a nine-pin SUB D9M connector. The disclosure can be applied to the making of interfaces capable of giving an electrical supply to an external device as well as to computers including such interfaces. The disclosure can be applied chiefly to the making of computers capable of working under the MS-DOS operating system and capable of providing a supply voltage to the MIDI interface by means of an RS 232 serial interface and a SUB D9M connector.

Abstract: A parallel-to-serial FIFO buffer device (100) employs a FIFO buffer (110) for storing words of data; a tap-shift-register portion (112); and a data-shift-register portion (116) for converting from parallel to serial format words of data stored in the FIFO buffer (110), tap-shift-register portion (112) controls the conversion process, receives (150) a serial-input-expansion (RSIX) input signal, and develops (170) a serial-output-expansion (RSOX) output signal. The serial-input-expansion input signal (150) and the serial-output-expansion output signal (170) permit the device (100) to be connected with one, or more, similar, device(s) for word length and/or depth expansion.

Abstract: A communication system including a communication control unit connected through a communication line to a different system, a high-ranking processor for control of the communication control unit, and a common memory used for transfer of data between the high-ranking processor and the communication control unit. The communication control unit includes a direct memory access controller and a line controller interconnected via a transmission-only path and a reception-only path. The communication control unit autonomously generates an information frame and stores it in the common memory. The direct memory access controller then reads the information frame and transfers it to the line controller via the transmission-only path in order to transmit the information frame to the different system.

Abstract: A symbol string collating apparatus includes a memory unit, a shift register, a collating unit, and an encoder. The memory unit includes memory circuits arranged in a matrix, stores a series of variable-length reference data with reference to a lower bit position of each column of the memory circuits, and stores specific data not including the reference data in a remaining portion. The shift register has the number of stages equal to the number of rows of the matrix and stores variable-length reference data to be collated which is externally input in series to the shift register in units of symbols. The collating unit collates the reference data stored in the shift register with the reference data stored in each column of the memory unit in units of bits. The encoder generates an output signal when at least a part of the reference data coincides with the reference data as a result of collating by the collating unit.

Abstract: In an instruction prefetching device for use in a data processing system, a history table (26) serves not only as a branch history table for memorizing branch predictions but also as a page-over history table for memorizing page-over information. Even when a prefetch real instruction address coincides in an instruction address register 23 with one of page last real instruction addresses, the history table produces a table hit signal and a page-over real instruction address which corresponds to the prefetch real instruction address in the page-over information kept in the history table.

Abstract: A Multiprocessor system is disclosed which includes a master processor, slave processor, and first and a second bank of memory for storing information to be operated on by the slave processor and a switch controlled by a master processor to switch the functional position of two banks of memory so that the slave processor switches from operating on information stored in the first bank to operating on information stored in the second bank and back under the control of the master processor.

Abstract: A method for the allocation of RAM memory space in a microcomputer environment allows for one or more terminate and stay resident (TSR) or other programs to be stored on a remote memory device in a way that preserves their accessability. The method includes the installation of a supervisory program which traps calls for a displaced program and transfers a portion of another program, such as an application-type program, in RAM to remote memory while retrieving the called displaced program from remote memory into the RAM space previously occupied by the transferred portion. The swap function is performed in a manner which preserves the integrity of the swapped program, and which allows operation of the application program to be halted such that it may be restarted without loss upon return from remote memory. In another aspect of the invention a communication TSR is simulated to allow data transfers to the TSR to be processed even if the TSR is in remote memory.

Abstract: Apparatus and method for assembling data read from a data storage DAT tape into data groups. A tape data processing circuit responsive to the playback of DAT tape for provides for each frame a serial frame information output including a frame header and frame data, and an associated subcode information output, the subcode information output being available in advance of the associated frame information. A processor responsive to the subcode information checks the validity of the subcode information and determines the destination group memory locations of the associated frame data, such destination group memory locations being group frame locations specified pursuant to valid subcode information or temporary storage areas for frames having invalid subcode information. DMA circuitry transfers the frame data to the destination group memory locations.

Abstract: In an information processing system comprising a main memory device, a plurality of processors, a system controller between the main memory device and the processors, and an extended buffer memory for carrying out a data transfer operation to and from the main memory device, the system controller comprises a communication lock circuit for selectively indicating a locked state and an unlocked state representative of a state of the extended buffer memory. The communication lock circuit is accessed to detect the state of the extended buffer memory each time when either a lock instruction or a lock release instruction is issued from each processor before a data transfer request is delivered from each processor to the extended buffer memory.

Abstract: A data cache capable of operation in a write-back (copyback) mode. The data cache design provides a mechanism for making the data cache coherent with memory, without writing the entire cache entry to memory, thereby reducing bus utilization. Each data cache entry is comprised of three items: data, a tag address, and a mixed size status field. The mixed size status fields provide one bit to indicate the validity of the data cache entry and multiple bits to indicate if the entry contains data that has not been written to memory (dirtiness). Multiple dirty bits provide a data cache controller with sufficient information to minimize the number of memory accesses used to unload a dirty entry. The data cache controller uses the multiple dirty bits to determine the quantity and type of accesses required to write the dirty data to memory. The portions of the entry being replaced that are clean (unmodified) are not written to memory.

Abstract: A processor pipeline control system and method provides a complete set of very simple and very fast pipeline control signals encompassing stalls and interrupts. Each pipeline stage has associated with it a signal called "LoadX", where X is the pipeline stage name, e.g., LoadID. Instead of signalling exceptional conditions in terms of the event, e.g., "cache miss", exceptional conditions are signalled within the processor by deasserting the LoadX signals required by that exception. When the pipeline control for one pipestage is deasserted, in order to prevent previous instructions from entering the stalled pipestage, the detector of the exceptional condition must deassert all LoadX control signals for stages previous to X as well.