Patents Examined by Kenneth B. Wells
  • Cyclic control of cells of an integrated circuit
    Patent number: 11626862
    Abstract: An embodiment of the present disclosure relates to a circuit of cyclic activation of an electronic function comprising a hysteresis comparator controlling the charge of a capacitive element powering the function.
    Type: Grant
    Filed: June 25, 2019
    Date of Patent: April 11, 2023
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Alexandre Tramoni, Jimmy Fort
  • Semiconductor device
    Patent number: 11621712
    Abstract: A semiconductor device includes a latch circuit including a first inverter configured to output a first signal based on an input signal, a second inverter configured to output a first clock signal based on a first strobe signal, a third inverter configured to output a second clock signal based on a second strobe signal, a first clock generation circuit configured to generate a third clock signal having transitions that are delayed with respect to the first clock signal, a second clock generation circuit configured to generate a fourth clock signal having transitions that are delayed with respect to the second clock signal, a fourth inverter configured to output an inversion signal of the first signal in accordance with the third and fourth clock signals, and a data latch circuit configured to latch an output signal of the fourth inverter.
    Type: Grant
    Filed: September 13, 2021
    Date of Patent: April 4, 2023
    Assignee: Kioxia Corporation
    Inventors: Yasuhiro Hirashima, Masaru Koyanagi, Yutaka Takayama
  • Electrostatic discharge clamp topology
    Patent number: 11611342
    Abstract: A clamping circuit comprises a first field-effect transistor (FET) having a gate, a source, and a drain, a diode, a first voltage source, and coupling circuitry configured to couple the first voltage source to the drain of the first FET and the diode to the source of the first FET.
    Type: Grant
    Filed: August 4, 2021
    Date of Patent: March 21, 2023
    Assignee: Skyworks Solutions, Inc.
    Inventor: Adrian John Bergsma
  • Gate driver having input and output sides galvanically isolated from one another
    Patent number: 11611332
    Abstract: A gate driver includes: an input pin for receiving switching control information from a controller; an output pin for driving a control terminal of a power transistor; a power supply pin for receiving power from an external supply; an input side electrically connected to the input pin; an output side electrically connected to the output pin and the power supply pin; and an isolation structure galvanically isolating the input side and the output side from one another. The output side is configured to transfer a fraction of the power received at the power supply pin to the input side over the isolation structure for powering the input side. The input side is configured to convey the switching control information received at the input pin to the output side over the isolation structure. A power electronic system that includes the gate driver is also described.
    Type: Grant
    Filed: December 3, 2021
    Date of Patent: March 21, 2023
    Assignee: Infineon Technologies Austria AG
    Inventor: Heiko Rettinger
  • Power switch drive circuit and device
    Patent number: 11611339
    Abstract: The invention relates to the field of power semiconductor devices. This invention discloses a drive circuit and device of a power switch. The input terminal of the drive circuit receives a pulse signal; the output terminal of the drive circuit is connected to a capacitor circuit. The capacitor circuit is used to provide a negative voltage for a first electrode of the power switch to turn off the power switch when the pulse signal is a turn-off signal; the drive circuit includes a capacitance adjustment unit. The capacitance adjustment unit includes a negative voltage adjustment element that can charge a capacitor whose voltage is lower than a predetermined voltage when the pulse signal is the turn-off signal.
    Type: Grant
    Filed: November 1, 2021
    Date of Patent: March 21, 2023
    Assignee: InventChip Technology Co., Ltd.
    Inventors: Zhong Ye, Danyang Zhu
  • Solid-state relay with isolator
    Patent number: 11611343
    Abstract: A solid-state relay circuit includes an isolator circuit, a first output terminal, a second output terminal, and an output switch. The output switch is coupled to the isolator circuit, and includes a first transistor, a second transistor, and a diode. The first transistor is coupled to the first output terminal. The second transistor is coupled to the first transistor and the second output terminal. The diode is coupled to the first transistor, the second transistor, and ground, and is configured to block current flow from ground to the first transistor and the second transistor. The isolator circuit is coupled to the output switch and is configured to activate the first transistor and the second transistor.
    Type: Grant
    Filed: January 27, 2022
    Date of Patent: March 21, 2023
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Navaneeth Kumar Narayanasamy, Manu Balakrishnan, Miroslav Oljaca
  • Level converting enable latch
    Patent number: 11606093
    Abstract: A level converting enable latch includes a level shifter circuit and a latch circuit. The level shifter circuit receives a first data input signal, and generates a first data output signal, wherein the first data input signal and the first data output signal have different voltage swings. The latch circuit sets a second data output signal in response to the first data output signal when a latch enable signal is set to a first logic value, and latches the second data output signal when the latch enable signal is set to a second logic value. The latch circuit includes a first control circuit. The first control circuit enables a latch feedback loop of the latch circuit when the latch enable signal is set to the second logic value, and disables the latch feedback loop of the latch circuit when the latch enable signal is set to the first logic value.
    Type: Grant
    Filed: July 7, 2021
    Date of Patent: March 14, 2023
    Assignee: MEDIATEK INC.
    Inventors: Wei-Min Hsu, Jen-Hang Yang
  • Control circuit, voltage source circuit, driving device, and driving method
    Patent number: 11606019
    Abstract: A control circuit includes a detection module configured to detect an operating condition of a semiconductor switching device; a determining module configured to determine a gate allowable voltage of the semiconductor switching device based on the operating condition; and an output module configured to output a control signal to a driving power supply circuit of the semiconductor switching device based on the gate allowable voltage, to control the driving power supply circuit to provide a gate on voltage that is not higher than the gate allowable voltage and that is positively correlated with the gate allowable voltage for the semiconductor switching device. When the operating condition of the semiconductor switching device becomes better, the gate allowable voltage of the semiconductor switching device is increased.
    Type: Grant
    Filed: October 6, 2021
    Date of Patent: March 14, 2023
    Assignee: Huawei Digital Power Technologies Co., Ltd.
    Inventors: Dong Chen, Lei Shi, Zhaohui Wang
  • Circuit for switching power supply and switching power supply device
    Patent number: 11601122
    Abstract: The present disclosure provides a power integrated circuit (IC) for a switching power supply device that generates an output voltage based on an input voltage. The circuit includes: a high-side transistor, disposed between an input terminal applied with the input voltage and a switch terminal; and a low-side transistor, disposed between the switch terminal and a ground terminal. A feedback control for turning on or off the transistor is performed based on a feedback voltage corresponding to the output voltage. A protection circuit is capable of performing a protection operation for turning on the high-side transistor or the low-side transistor regardless of the feedback control based on a switch voltage at the switch terminal and the input voltage, based on a backflow current from the ground terminal to the switch terminal, or based on the input voltage and a predetermined determination voltage.
    Type: Grant
    Filed: December 20, 2021
    Date of Patent: March 7, 2023
    Assignee: Rohm Co., Ltd.
    Inventor: Shidong Guan
  • Input/output (I/O) circuit with dynamic full-gate boosting of pull-up and pull-down transistors
    Patent number: 11595042
    Abstract: An aspect of the disclosure relates to an apparatus including an output driver, including: a first p-channel metal oxide semiconductor field effect transistor (PMOS FET); a second PMOS FET coupled in series with the first PMOS FET between an upper voltage rail and an output; a first n-channel metal oxide semiconductor field effect transistor (NMOS FET); and a second NMOS FET coupled in series with the first NMOS FET between the output and a lower voltage rail; a first predriver coupled to gates of the first and second PMOS FETs and first and second NMOS FETs; and a second predriver coupled to the gates of the first and second PMOS FETs and first and second NMOS FETs.
    Type: Grant
    Filed: November 15, 2021
    Date of Patent: February 28, 2023
    Assignee: QUALCOMM INCORPORATED
    Inventors: Wilson Jianbo Chen, Chiew-Guan (Kelvin) Tan
  • Communication apparatus and method thereof
    Patent number: 11588518
    Abstract: An apparatus includes a rectifier having a first input coupled to a first terminal of a receiver coil and a second input coupled to a second terminal of the receiver coil, wherein the rectifier is configured to convert an alternating current voltage into a direct current voltage, a first communication network connected to the first input of the rectifier, and a second communication network connected to the second input of the rectifier, wherein the first communication network and the second communication network are controlled independently to adjust a gain of a wireless power transfer system.
    Type: Grant
    Filed: May 19, 2021
    Date of Patent: February 21, 2023
    Assignee: NuVolta Technologies (Hefei) Co., Ltd.
    Inventor: Zhijun Luo
  • Level shifter
    Patent number: 11581878
    Abstract: A level shifter includes a control circuit and a bias circuit. The control circuit receives a bias voltage, a first signal associated with a first voltage domain, and supply voltages associated with a second voltage domain, and outputs a second signal that is associated with the second voltage domain. The bias circuit generates the bias voltage that is indicative of the duty cycle of the second signal, and provides the bias voltage to the control circuit to control the duty cycle of the second signal. The duty cycle of the second signal is controlled such that a difference between a duty cycle of the first signal and an inverse of the duty cycle of the second signal is less than a tolerance limit.
    Type: Grant
    Filed: October 8, 2021
    Date of Patent: February 14, 2023
    Assignee: NXP B.V.
    Inventors: Sanjay Kumar Wadhwa, Saurabh Goyal, Divya Tripathi
  • Systems and methods for detecting local oscillator leakage and image tone in I/Q mixer based transceivers
    Patent number: 11581852
    Abstract: According to one embodiment, a transceiver includes: a radio transmitter including a power amplifier; a detector circuit including: a squaring circuit configured to receive an output of the power amplifier of the radio transmitter and configured to produce an output current; and a DC current absorber electrically connected to an output terminal of the squaring circuit.
    Type: Grant
    Filed: October 26, 2021
    Date of Patent: February 14, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hariharan Nagarajan, Ashutosh Verma, Chung Lau, Tienyu Chang
  • Switching apparatus and switching method
    Patent number: 11581890
    Abstract: Provided is a switching apparatus, including: a first semiconductor switching device of IGBT, and a second semiconductor switching device of a different type from IGBT, which are electrically connected in parallel; and a control unit configured to turn on the second semiconductor switching device before the first semiconductor switching device, wherein a maximum rated current of the second semiconductor switching device is greater than a maximum rated current of the first semiconductor switching device.
    Type: Grant
    Filed: November 25, 2021
    Date of Patent: February 14, 2023
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Harunobu Ikeda
  • Skew detection system and method to remove unwanted noise due to skewed signals
    Patent number: 11573268
    Abstract: Various embodiments relate to a skew detector circuit, including: a logic circuit having two inputs configured to generate a logic 1 output when the two inputs have a logic 0 value and generator a logic 0 output when the two input have a logic 1 value; a first level shifter configured to increase the output of the logic circuit to a higher voltage; a second level shifter configured to increase the output of the first level shifter to a higher voltage; and a voltage regulator configured to produce a first voltage for the logic circuit, a second voltage for the first level shifter, and a third voltage for the second level shift.
    Type: Grant
    Filed: September 14, 2021
    Date of Patent: February 7, 2023
    Assignee: NXP USA, Inc.
    Inventors: Siamak Delshadpour, Xu Zhang, Xiaoqun Liu, Kenneth Jaramillo
  • Semiconductor structure and operation circuit
    Patent number: 11574997
    Abstract: A semiconductor structure including a substrate, a first well, a second well, a first doped region, a second doped region, a gate electrode, an insulating layer, a field plate, and a tunable circuit is provided. The first and second wells are formed on the substrate. The first doped region is formed in the first well. The second doped region is formed in the second well. The gate electrode is disposed over the substrate. The gate electrode, the first doped region, and the second doped region constitute a transistor. The insulating layer is disposed on the substrate and overlaps the gate electrode. The field plate overlaps the insulating layer and the gate electrode. The tunable circuit provides either a first short-circuit path between the field plate and the gate electrode, or a second short-circuit path between the field plate and the first doped region.
    Type: Grant
    Filed: August 2, 2021
    Date of Patent: February 7, 2023
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Shao-Chang Huang, Li-Fan Chen, Ching-Ho Li, Gong-Kai Lin, Chieh-Yao Chuang
  • Management of multiple switching-synchronized measurements using combined prioritized measurement and round-robin sequence measurement
    Patent number: 11575369
    Abstract: A method for operating a gate driver system includes measuring a first parameter according to a first priority schedule synchronously to a first edge of a switching signal generated by a gate driver integrated circuit and having a variable duty cycle. The method includes after measuring the first parameter of the gate driver system and prior to a second edge of the switching signal, measuring at least a second parameter of the gate driver system according to a first round-robin schedule synchronously to the first edge of the switching signal.
    Type: Grant
    Filed: December 7, 2021
    Date of Patent: February 7, 2023
    Assignee: Skyworks Solutions, Inc.
    Inventors: James Edward Heckroth, Ion Constantin Tesu
  • Electronic device performing power gating operation
    Patent number: 11575375
    Abstract: An electronic device includes a driving control signal generation circuit configured to generate first and second driving control signals and a driving switching control signal. The electronic device also includes a switching control signal driving circuit configured to drive a switching control signal to a first voltage on the basis of the first driving control signal and the driving switching control signal or drive the switching control signal to a second voltage on the basis of the second driving control signal, depending on whether a power-down mode is performed.
    Type: Grant
    Filed: October 12, 2021
    Date of Patent: February 7, 2023
    Assignee: SK hynix Inc.
    Inventor: Yun Seok Hong
  • Variable capacitance circuit for phase locked loops
    Patent number: 11569814
    Abstract: A variable capacitance circuit may operate a Metal Oxide Semiconductor (MOS) transistor or other semiconductor device to switch a capacitor in and out. Several circuits may be combined in a parallel network having offset bias voltages, such that the combined network may produce a variable capacitance over a large voltage range. The variable capacitance circuit may be incorporated into a phase locked loop (PLL) circuit where similar devices may be configured to produce a voltage reference as part of the PLL circuitry. Such a circuit may be immune to temperature, process, or voltage variances, since the current pulse magnitude times the low pass filter resistance times the sensitivity of a controlled voltage oscillator can be held constant.
    Type: Grant
    Filed: October 15, 2021
    Date of Patent: January 31, 2023
    Assignee: Analog Bits, Inc.
    Inventors: Alan C. Rogers, Raghunand Bhagwan Iyengar
  • Laser radar device
    Patent number: 11561293
    Abstract: A light receiving unit receives a pulsed optical signal arriving from a search region. A branching unit generates, from a received light signal, a plurality of branch signals having signal intensities proportional to a signal intensity of the received light signal and different from one another. A conversion unit converts, from analog to digital, a signal fed via the individual path selected by a selection unit, and in accordance with a result of the conversion, a processing unit generates information regarding an object reflecting the optical signal. A control unit causes the selection unit to select one of the individual paths for which a determination unit determines that a magnitude of the fed signal is within an input range of the conversion unit and which provides the highest gain.
    Type: Grant
    Filed: April 28, 2020
    Date of Patent: January 24, 2023
    Assignee: DENSO CORPORATION
    Inventor: Shunsuke Kimura