Abstract: A semiconductor integrated circuit includes: a first circuit having a plurality of scan chains; a second circuit connected with input/output signals of the first circuit; and a third circuit connected with the second circuit through the first circuit. The plurality of scan chains comprises a first scan chain that contains flip-flops whose input/output signals are connected with the second circuit, and a second scan chain that does not contain any flip-flop whose input/output signal is connected with the second circuit. The flip-flops operate as a shift register at a scan path test, and when the third circuit exchanges signals with the second circuit through the flip-flops of the first scan chain, the second scan chain of the first circuit operates as a shift register.

Abstract: An integrated device comprises a functional circuit, a test circuit for testing the functional circuit and for providing an error data item and a register element for storing the error data item and for outputting the error data item at an error data output of the integrated device responsive to an output signal. The register element is connected to a data input of the integrated device in order to accept a data item, which is applied to the data input, responsive to the output signal.

Abstract: The present disclosure describes using the JTAG Tap's TMS and/or TCK terminals as general purpose serial Input/Output (I/O) Manchester coded communication terminals. The Tap's TMS and/or TCK terminal can be used as a serial I/O communication channel between; (1) an IC and an external controller, (2) between a first and second IC, or (3) between a first and second core circuit within an IC. The use of the TMS and/or TCK terminal as serial I/O channels, as described, does not effect the standardized operation of the JTAG Tap, since the TMS and/or TCK I/O operations occur while the Tap is placed in a non-active steady state.

Abstract: Implementations are presented herein that relate to improved Joint Test Action Group (JTAG) compatible devices.

Abstract: A system and method for increasing the yield of integrated circuits containing memory partitions the memory into regions and then independently tests each region to determine which, if any, of the memory regions contain one or more memory failures. The test results are stored for later retrieval. Prior to using the memory, software retrieves the test results and uses only the memory sections that contain no memory failures. A consequence of this approach is that integrated circuits containing memory that would have been discarded for containing memory failures now may be used. This approach also does not significantly impact die area.

Abstract: An integrated circuit with a scan testing circuit which enables reducing power consumption in normal operation mode is provided. A power-supply controller applies a power-supply voltage to internal and external transmission circuits in scan test mode and stops applying the power supply voltage in normal operation mode. Thus, power consumption associated with operations of the internal and external transmission circuits is eliminated, thereby reducing power consumption in normal operation mode.

Abstract: A built-in, at-speed BERT is provided that may be part of high-speed serial interface circuitry implemented on an integrated circuit. The built-in, at-speed BERT takes advantage of an existing clock data recovery (CDR) dual-loop architecture and built-in self test (BIST) circuitry. The built-in, at-speed BERT provides a low-cost solution for production testing of high-speed serial links, facilitating jitter analysis and evaluation of pre-emphasis and equalization performance. This further allows adaptation of pre-emphasis and equalization.

Abstract: A test apparatus that tests a device under test is provided. The test apparatus includes: a main memory that stores a test data row for testing the device under test; a cache memory that caches the test data row read from the main memory; a pattern generation control section that reads each test data which is not aligned in units of word being a data transfer unit of the main memory and writes the same to cache entries different from each other in the cache memory for each test data; and a pattern generating section that sequentially reads the test data stored of each cache entry in the cache memory and generates a test pattern for testing the device under test.

Abstract: A method of programming a programmable logic device (PLD), in accordance with an embodiment, includes receiving trigger unit information of a logic analyzer via a software interface for monitoring internal PLD signals and providing trigger unit output signals based on the internal PLD signals for the corresponding trigger units; and receiving trigger expression information of the logic analyzer via the software interface as a text string of logic operators and operands, wherein the operands represent the trigger unit output signals. The method may further include generating configuration data based on the trigger unit information and the trigger expression information; and providing the configuration data to the PLD, wherein a trigger expression based on the trigger expression information is stored within memory of the PLD.

Abstract: A test system for performing tests on devices under test (DUTs) includes a storage device storing test data for performing the tests on the DUTs, a shared processor for generating the test data, storing the test data in the storage device and generating a test control signal including one or more test instructions for executing the tests, and, for each DUT, a dedicated processor configured to receive a test control signal from the shared processor, and in response to the test control signal, transfer the test data for one of the test instructions to the DUT to execute that test instruction and verify the completion of that test instruction.

Abstract: A programmable logic device includes a configuration memory, a checker, and a redundant-logic detector. An array of programmable logic and interconnect resources is configurable to implement a selected user design. The configuration memory stores configuration data that configures the array of programmable logic and interconnect resources to implement the specified user design. A checker calculates a sequence of checksums from the configuration data that is stored in the configuration memory. A redundant-logic detector indicates corruption of the configuration data stored in the configuration memory in response to at least two consecutive checksums in the sequence not matching a reference value.

Abstract: A method and apparatus for synchronizing plural test devices coupled to a host. A counter of each of the devices is initialized, and each of the counters is incremented, such as by a periodic signal indicating a start of a data stream. An action, typically either a source signal or a measurement signal, is triggered when a respective counter reaches a programmed counter value.

Abstract: A method and apparatus allows externally selecting a functional operation mode or one of a plurality of test operation modes of an electronic device, and in particular a volatile or non-volatile memory device, without the need for additional device connections. One variation of the method and apparatus allows unlimited switching between modes. Another variation of the method and apparatus limits test operation mode selection except at the time of powering up of the device. In either variation, mode selection is based on internally detected stimulus externally applied to the device that would not be present during normal functional operation of the device. Operation of the present invention is essentially transparent in applications where test operations are not utilized, making a device incorporating the present invention compatible with previous versions of the device where the present invention and test operation modes, such as IEEE P1581 and BIST, were not included.

Abstract: The present invention provides a method and apparatus for efficiently loading values into scan and non-scan memory elements. First, the network used to distribute control signals to the memory elements is cleared. Second, the desired values are loaded into the scan memory elements. Third, the values from the scan memory elements are propagated to the non-scan memory elements.

Abstract: An eFuse data alignment verification mechanism is provided. Alignment latches are provided in a series of latch units of a write scan chain and a logic unit is coupled to the alignment latches. A sequence of data that is scanned-into the series of latch units of the write scan chain preferably includes alignment data values. These alignment data values are placed in positions within the sequence of data that, if the sequence of data is properly scanned-into the series of latch units, cause the data values to be stored in the alignment latches. The logic unit receives data signals from the alignment latches and determines if the proper pattern of data values is stored in the alignment latches. If the proper pattern of data values is present in the alignment latches, then the data is aligned and a program enable signal is sent to the bank of eFuses.

Abstract: A path data transmission unit in which, if one of a normal path for handling normal data and a test path for handling test data is selected, the other path is disabled to reduce power consumption; includes an edge detector, a first path data transmission block, and a second path data transmission block. The edge detector detects an edge of a test enable signal that indicates a normal operation mode or a test mode and transmits an edge detection signal. The first path data transmission block transmits a first path data in response to the test enable signal, the edge detection signal, a clock signal, normal data and a second path data. The second path data transmission block transmits the second path data in response to the test enable signal, the clock signal, and test data.

Abstract: A testing circuit includes a signal generator operative to provide a control signal in response to a reference clock signal. The control signal may include both alignment and timing information operative to synchronize the timing and output of the signal generator with a device under test. A clock recovery instrument is electrically coupled to the signal generator. The clock recovery instrument generates the reference clock signal in response to a clock signal from the device under test. The reference clock signal is synchronized with the clock signal from the device under test such that signal generator operation is synchronized with the device under test independent of the behavior of the device under test.

Abstract: A semiconductor integrated circuit having an internal circuit which is tested based on a scanning method is provided. The internal circuit has: memory elements including a first memory element and a second memory element; combinational circuits including a first combinational circuit receiving an external input data, a second combinational circuit outputting an external output data and a third combinational circuit; a first selection circuit; and a second selection circuit. The first selection circuit receives the external input data and a stored data held by the first memory element, and outputs any of them to the first combinational circuit. The second selection circuit receives the external output data output from the second combinational circuit and an operation result data output from the third combinational circuit, and outputs any of them to the second memory element.

Abstract: A method and system for performing diagnostic tests on a real-time system controlled by a state machine. A sequence of states recorded as the state machine operates is used to determine error conditions. The sequence of states is compared to expected sequences of states to determine what, if any, errors have occurred. If the real-time system, such as a transceiver in a communication system, has adaptive components, the status of the adaptive components is used to estimate the condition of any external systems coupled to the real-time system.

Abstract: A method and apparatus for testing a data transfer system. The method comprises the steps of storing a first table, the first table noting at least a time of issuance of at least one command and a time of completion of the command and comparing the time of issuance of the command and the time of completion of the command. A timeout condition is registered if the processor determines that a time longer than a predetermined time elapsed between the time of issuance of the command and the time of completion of the command.