Abstract: A modular subtraction instruction for execution on a microprocessor having at least one register. The instruction includes opcode bits for designating the instruction and operand bits for designating at least one register storing an offset index, a decrement value, and an address index. When the modular subtraction instruction is executed on the microprocessor, the address index is modified by the decrement value if the address index is not zero and is modified by the offset index if the address index is zero. For example, the address index is repeatedly decremented using the decrement value until it reaches zero, and then the address index is reset back to the offset index. The operand bits may include multiple fields identifying multiple registers selected from the general purpose registers of the microprocessor. The modular subtraction instruction enables access to a buffer in memory in circular fashion by virtue of its operation.

Abstract: In an embodiment, when a removable storage device is removably coupled to a host, the removable storage device indicates that it is non-removable to the host. The removable storage device may include a user-created secure storage area.

Abstract: Embodiments of apparatuses, articles, methods, and systems for associating identifiers with memory locations for controlling memory accesses are generally described herein. Other embodiments may be described and claimed.

Abstract: A memory subsystem includes volatile memory and nonvolatile memory, and logic to interrupt a power down save operation of the memory subsystem upon detection of a restoration of system power, and to enable use of the memory subsystem by the system if sufficient nonvolatile memory capacity of the memory subsystem is available to backup an amount of the volatile memory capacity of the memory subsystem.

Abstract: A disk array system having first and second housings and a controller for controlling the first and second housings. Fiber channel hard disk drives are received in the first housing, and serial ATA hard disk drives are received in the second housing. When reading data stored in a serial ATA hard disk drive in the second housing, the controller reads a plurality of pieces of data including the data to be read and parity data for the plurality of pieces of data from all the hard disk drives of an RAID group to which the hard disk drive storing the data to be read belongs. Thus, the controller examines whether the plurality of pieces of data including the data to be read are written in the hard disk drives with erroneous contents or not.

Abstract: Methods and apparatuses to calibrate read/write memory accesses through data buses of different lengths via advanced memory buffers. One embodiment includes an advanced memory buffer (AMB) having: a plurality of ports to interface respectively with a plurality of data buses; a port to interface with a common clock bus for the plurality of data buses; and an adjustable circuit coupled with the plurality of ports to level delays on the plurality of data buses. In one embodiment, the data buses have different wire lengths between the dynamic random access memory (DRAM) memory chips and the advanced memory buffer (AMB).

Abstract: Cache memory systems and methods thereof are provided. A first example cache memory system may include a central processing unit (CPU) and a first memory, a second memory positioned between the CPU and the first memory and storing at least one block of the first memory and a block quantity determination unit which determines a block quantity indicating a number of blocks of the first memory to be stored in the second memory. A second example cache memory system, including a cache memory receiving a request to provide data associated with an input address, determining whether the input address is included in the cache memory, loading a plurality of adjacent data blocks, associated with the input address, from the main memory if the input address is not included within the cache memory.

Abstract: An asynchronously pipelined SDRAM has separate pipeline stages that are controlled by asynchronous signals. Rather than using a clock signal to synchronize data at each stage, an asynchronous signal is used to latch data at every stage. The asynchronous control signals are generated within the chip and are optimized to the different latency stages. Longer latency stages require larger delays elements, while shorter latency states require shorter delay elements. The data is synchronized to the clock at the end of the read data path before being read out of the chip. Because the data has been latched at each pipeline stage, it suffers from less skew than would be seen in a conventional wave pipeline architecture. Furthermore, since the stages are independent of the system clock, the read data path can be run at any CAS latency as long as the re-synchronizing output is built to support it.

Abstract: A processor of an apparatus in an example upon a failure of an earlier attempt to directly acquire ownership of an access coordinator for a resource shared with one or more additional processors, locally determines an amount to delay a later attempt to directly acquire ownership of the access coordinator. Upon a failure of the later and/or a subsequent attempt to directly acquire ownership of the access coordinator the processor would enter into an indirect waiting arrangement for ownership of the access coordinator.

Abstract: A cache memory system includes a cache memory and a block replacement controller. The cache memory may include a plurality of sets, each set including a plurality of block storage locations. The block replacement controller may maintain a separate count value corresponding to each set of the cache memory. The separate count value points to an eligible block storage location within the given set to store replacement data. The block replacement controller may maintain for each of at least some of the block storage locations, an associated recent access bit indicative of whether the corresponding block storage location was recently accessed. In addition, the block replacement controller may store the replacement data within the eligible block storage location pointed to by the separate count value depending upon whether a particular recent access bit indicates that the eligible block storage location was recently accessed.

Abstract: A system and a method for configuration and management of flash memory is provided, including a flash memory, a virtual memory region, and a memory logical block region. The flash memory includes a plurality of physical erase units. Each physical erase unit is configured to include at least a consecutive segment, and each segment is configured to include at least a consecutive frame. Each frame is configured to include at least a consecutive page. Each virtual memory region is configured to include a plurality of areas, and each area is configured to include at least a virtual erase unit. The memory logical block region is configured to include a plurality of clusters, and each cluster includes at least a consecutive memory logical block.

Abstract: Methods, systems, and computer program products for providing memory management with constant defragmentation time are disclosed. According to one aspect, the subject matter described herein includes a method for memory management. The method includes dividing memory to be allocated into a plurality of pages of equal size P, wherein P is an integer. The method also includes designating each page for holding records of a respective predetermined record size, at least some of the respective predetermined record sizes being different from each other, wherein, when filled, each page holds records of its respective predetermined record size and wherein at least some of the pages hold a remainder record having a size based on the page size P and the space allocated for the maximum number of records of the page's respective predetermined record size that will fit within the page. The method also includes allocating memory so that each page is populated with records of its respective predetermined record size.

Abstract: Provided are a method, system, and article of manufacture for providing a process exclusive access to a page including a memory address to which a lock is granted to the process. A request is received for a memory address in a memory device from a requesting process. A lock is granted to the requested memory address to the requesting process. The requesting process is provided exclusive access to a page including the requested memory address for a page access time period. The exclusive access to the page provided to the requesting process is released in response to an expiration of the page access time period.

Abstract: Representative is a computer-implemented method of detecting a buffer overflow condition. In accordance with the method, a destination address for a computer process' desired right operation is received and a determination is made as to whether the destination address is within an illegitimate writable memory segment within the process' virtual address space (VAS). If so, the process is preferably alerted of the potential buffer overflow condition. A determination may also be made as to whether the destination address is legitimate, in which case the process may be informed of the memory segment which corresponds to the destination address.

Abstract: Access to non-volatile memory is controlled when a first data segment is loaded in the non-volatile memory from a hard disk, a weight is calculated for the first data segment stored in the non-volatile memory based on at least one of the access frequency, the access recency, and the size of the first data segment, and the calculated weight is stored in a weight table. A removal rank is calculated for the first data segment based on at least one weight stored in the weight table, a determination is made as to whether a storage capacity of the non-volatile memory is utilized above a predetermined threshold, and a data segment is removed from the non-volatile memory based on a removal rank associated with the data segment.

Abstract: A data storage system having a packet switching network, a cache memory, and a plurality of directors, one portion of such directors being adapted for coupling to a host computer/server and another portion of the directors being adapted for coupling to a bank of disk drives. The plurality of directors and cache memory are interconnected through the packet switching network. Each one of the directors is adapted to transmit different types of information packets to another one of the directors through the network. Each one of the directors is adapted to transmit and receive different types of information packets to another one of the directors or cache memories through the packet switching network. Each one of the cache memories is adapted to receive and transmit different types of information packets to one of the directors through the packet switching network. One type of information packet requires a different degree of latency than another type of information packet.

Abstract: A method, system, device, and article of manufacture for use in a computer memory system utilizing multiple page types, for handling a memory resource request. In a accordance with the method of the invention, a request is received for allocation of pages having a first page type. The first page type has a specified allocation limit. A determination is made in response to the page allocation request of whether the number of allocated pages of the first page type exceeds or is below the allocation limit. In response to determining that the number of allocated pages of said first page type is below the allocation limit, the virtual memory manager enables allocation of pages for the request to exceed the allocation limit.

Abstract: A system and method comprising a non-volatile memory including one or more memory blocks to store data, a controller to allocate one or more of the memory blocks to store data, and a wear-leveling table populated with pointers to unallocated memory blocks in the non-volatile memory, the controller to identify one or more pointers in the wear-leveling table and to allocate the unallocated memory blocks associated with the identified pointers for the storage of data.

Abstract: To provide a technique whereby a plurality of types of storage media can be utilized in an efficient manner. A management apparatus includes a file manager that manages files within an integrated memory area that includes a first memory area composed of at least a part of the first type of storage medium and a second memory area composed of at least a part of the second type of storage medium. The file manager builds one filesystem on the integrated memory area, in consideration of a range of the first memory area and a range of the second memory area.

Abstract: In one embodiment, the invention comprises a flash-media controller used for writing new data from an external system to a local flash-memory device. The newly written data may replace old data previously written to the flash-memory device, and may be written directly to unused locations within the flash-memory device. The flash-media controller may comprise a table of block descriptors and sector descriptors used to track specified characteristics of each block and sector of the flash-memory device, thereby allowing for write sequences to non-contiguous sectors within a block. Accordingly, copy operations may be deferred under the expectation that they will eventually become unnecessary, thereby designating old data as having become stale.