Patents Examined by Kevin L. Ellis
  • Test data generator, test system and method thereof
    Patent number: 7610530
    Abstract: A test data generator, test system and method thereof are provided. In the example method, parallel test data may be received at a first data rate. The received parallel test data may be converted into serial test data at a second data rate. Noise (e.g., jitter noise, level noise, etc.) may be selectively inserted into the converted serial test data. The noise inserted into the serial test data, which may be configured to operate at a higher data rate than the parallel test data, may allow a device to be tested with higher data-rate test data. The example method may be performed by the example test data generator and/or by the example test system.
    Type: Grant
    Filed: August 23, 2006
    Date of Patent: October 27, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin-Mo Jang, Young-Bu Kim, Du-Sik Yoo, Byung-Wook Ahn
  • Auto suggestion of coding error correction
    Patent number: 7607066
    Abstract: Suggested corrections for a code error are provided by a compiler or code editor, for example. Thus, there is much less ambiguity about how an error should be corrected. Preferably, a predetermined number of suggested corrections are presented to the user (e.g., up to three suggestions), and the user can choose a desired suggested correction. Corrections for a given error can be made, not only at the location of the error, but throughout the code document, or other files in the user's solution. Furthermore, by undoing one correction and trying another, the user can go through all of the suggested corrections to determine which suggestion would be most preferable.
    Type: Grant
    Filed: June 26, 2002
    Date of Patent: October 20, 2009
    Assignee: Microsoft Corporation
    Inventors: Matthew Wayne Gertz, Sam Spencer, Ernest Kien-Keung Tong, Li Zhang
  • Semiconductor memory device and method of testing the same
    Patent number: 7607055
    Abstract: A semiconductor memory device includes at least one first built in self test (BIST) circuit configured to generate test pattern data, and at least one second BIST circuit configured to receive the test pattern data as received test pattern data and compare the received test pattern data to the test pattern data.
    Type: Grant
    Filed: February 6, 2006
    Date of Patent: October 20, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dae-Hee Jung, Chul-Woo Park, Seung-Young Seo
  • Method and system for conservatively managing store capacity available to a processor issuing stores
    Patent number: 7606979
    Abstract: Method and system for conservatively managing store capacity available to a processor issuing stores are provided and described. In particular, a counter mechanism is utilized, whereas the counter mechanism is incremented or decremented based on the occurrence of particular events.
    Type: Grant
    Filed: December 12, 2006
    Date of Patent: October 20, 2009
    Inventors: Guillermo Rozas, Alexander Klaiber, David Dunn, Paul Serris, Lacky Shah
  • Method and apparatus for concurrent and independent data transfer on host controllers
    Patent number: 7603514
    Abstract: An access detector detects an access type of an access to one of a plurality of serial ports interfacing to serial storage devices. The access is intended to one of a plurality of parallel channels interfacing to parallel storage devices via task file registers of the parallel channels. A mapping circuit maps the serial ports to the parallel channels. A state machine emulates a response from the one of the parallel channels based on the access type and the mapped serial ports.
    Type: Grant
    Filed: March 31, 2005
    Date of Patent: October 13, 2009
    Assignee: Intel Corporation
    Inventor: Eng Hun Ooi
  • Test apparatus and electronic device
    Patent number: 7603604
    Abstract: A test apparatus that tests a device under test is provided. The test apparatus includes: a pattern memory that stores in a compression format a test instruction sequence to define a test sequence for testing the device under test; an expanding section mat expands in a non-compression format the test instruction sequence read from the pattern memory; an instruction cache that caches the test instruction sequence which is expanded by the expanding section; a pattern generating section that sequentially reads instructions stored in the instruction cache and executes the same to generate a test pattern for the executed instruction; and a signal output section that generate a test signal based on the test pattern and provides the same to the device under test.
    Type: Grant
    Filed: April 9, 2007
    Date of Patent: October 13, 2009
    Assignee: Advantest Corporation
    Inventors: Tatsuya Yamada, Kiyoshi Murata
  • Configurable memory architecture with built-in testing mechanism
    Patent number: 7603603
    Abstract: A configurable memory architecture includes a built-in testing mechanism integrated in said memory to support very efficient built-in self-test in Random Access Memories (RAMs) with greatly reduced overhead, in terms of area and speed. Memories can fail at high speed due to glitches (unwanted pulses which can at times behave as invalid clocks and destroy the functionality of synchronous systems) produced in decoding, the slow precharge of bitlines or the slow sensing of the sense amplifiers. The memory architecture incorporates structured DFT techniques to separately detect these failures.
    Type: Grant
    Filed: May 26, 2006
    Date of Patent: October 13, 2009
    Assignee: STMicroelectronics PVT. Ltd.
    Inventor: Prashant Dubey
  • Virtual machine spanning multiple computers
    Patent number: 7596654
    Abstract: In one embodiment, a virtual NUMA system may be formed from multiple computer systems coupled to a network such as InfiniBand, Ethernet, etc. Each computer includes one or more software modules which present the resources of the computers as a virtual NUMA machine. A single instance of a guest operating system executes on the virtual NUMA machine. The guest operating system is designed to execute on a NUMA system and executes without modification on the virtual machine. The memory model of the virtual NUMA machine includes a single writer, multiple reader memory model.
    Type: Grant
    Filed: January 26, 2006
    Date of Patent: September 29, 2009
    Assignee: Symantec Operating Corporation
    Inventor: Kai C. Wong
  • Using a processor to program a semiconductor memory
    Patent number: 7594065
    Abstract: A memory programmer may be coupled through a first processor and a physical interface to a semiconductor memory to be programmed. The interface may be the same interface that allows two separate processors in a multiprocessor memory to communicate with one another in one embodiment. Thus, an independent memory bus coupled directly to the memory components to be programmed may be eliminated, reducing form factor, decreasing costs, and increasing manufacturing throughput in some embodiments of the present invention.
    Type: Grant
    Filed: July 14, 2006
    Date of Patent: September 22, 2009
    Assignee: Marvell International Ltd.
    Inventor: Peter D. Mueller
  • Method for changing data of a data block in a flash memory having a mapping area, a data area and an alternative area
    Patent number: 7594062
    Abstract: A method for flash memory management where, if changing of data of a data block recorded in a data area is requested, recording the data block having changed data in an alternative area and recording mapping information representing an address of the data block recorded in the alternative area in a mapping area. If changing of data of the data block recorded in the alternative area is requested, recording a data block having changed data in the data area and deleting the mapping information representing the address recorded in the alternative area from the mapping area. If the mapping information on the data block exists in the mapping area, data is read from the data block in the alternative area, and if the mapping information on the data block does not exist in the mapping area, data is read from the data block at the original address in the data area.
    Type: Grant
    Filed: July 25, 2003
    Date of Patent: September 22, 2009
    Assignees: Samsung Electronics., Ltd., Zeen Information Technologies, Inc.
    Inventors: Ji-hyun In, Dong-hee Lee, Bum-soo Kim, Sung-kwan Kim, Song-ho Yoon
  • Storage system and storage control device
    Patent number: 7594083
    Abstract: The storage system according to the present invention allows the number of host connections to be increased by connecting a plurality of storage control devices so that commands and data can be directly exchanged between each storage control device. The first storage control device has a plurality of controllers, and the second storage control device also has a plurality of controllers. Within each storage control device, controllers are connected by inter-controller communication paths. Also, between storage control devices, controllers belonging to different storage control devices are connected by inter-device communication paths. If the subject of processing of a command received by one storage control device is under the control of another storage control device, the command is transferred from the one storage control device to the other storage control device via the inter-device communication path.
    Type: Grant
    Filed: September 6, 2006
    Date of Patent: September 22, 2009
    Assignee: Hitachi, Ltd.
    Inventors: Midori Kurokawa, Azuma Kano
  • System and method for an asynchronous data buffer having buffer write and read pointers
    Patent number: 7594088
    Abstract: A system and method for facilitating the adjustment of timing parameters between a memory controller operating in a first clock domain and a memory device operating in a second clock domain. A write pointer and a read pointer are monitored to provide a write-read pointer offset representing the timing between when read data is made available by the memory device and when the read data is retrieved by the memory controller. Based on the write-read pointer offset, adjustment to different timing parameters can be made.
    Type: Grant
    Filed: May 4, 2006
    Date of Patent: September 22, 2009
    Assignee: Micron Technology, Inc.
    Inventor: Paul A. LaBerge
  • D-cache miss prediction and scheduling
    Patent number: 7594078
    Abstract: A method and apparatus for D-cache miss prediction and scheduling is provided. In one embodiment, execution of an instruction in a processor is scheduled. The processor may have at least one cascaded delayed execution pipeline unit having two or more execution pipelines that execute instructions in a common issue group in a delayed manner relative to each other. The method includes receiving an issue group of instructions, determining if a first instruction in the issue group resulted in a cache miss during a previous execution of the first instruction, and if so, scheduling the first instruction to be executed in a pipeline in which execution is delayed with respect to another pipeline in the cascaded delayed execution pipeline unit.
    Type: Grant
    Filed: February 9, 2006
    Date of Patent: September 22, 2009
    Assignee: International Business Machines Corporation
    Inventor: David A. Luick
  • Cache scanning system and method
    Patent number: 7590813
    Abstract: A method includes stalling a cache flush instruction to flush a cache; determining that the cache comprises a file that has been infected with malicious code, and terminating the cache flush instruction to prevent the cache from being flushed to disk. By preventing copying of the infected file from the cache to disk, the malicious code is prevented from being propagated to disk. Accordingly, the malicious code is detected and defeated without having the malicious code be present on disk. Thus, detection of an infected file on disk and the repair of the infected file on disk are unnecessary and obviated.
    Type: Grant
    Filed: August 9, 2004
    Date of Patent: September 15, 2009
    Assignee: Symantec Corporation
    Inventor: Peter Szor
  • Flash memory systems utilizing direct data file storage
    Patent number: 7590795
    Abstract: Host system data files are written directly to a large erase block flash memory system with a unique identification of each file and offsets of data within the file but without the use of any intermediate logical addresses or a virtual address space for the memory. Directory information of where the files are stored in the memory is maintained within the memory system by its controller, rather than by the host.
    Type: Grant
    Filed: August 2, 2006
    Date of Patent: September 15, 2009
    Assignee: SanDisk Corporation
    Inventors: Alan W. Sinclair, Barry Wright
  • Disk array apparatus and method for controlling the same
    Patent number: 7587548
    Abstract: An apparatus which includes a controller and a plurality of disk drives. The controller has a communication control unit for accepting a data input/output request, a disk controller unit for controlling a disk drive, and a cache memory for temporarily storing data transferred between the communication control unit and the disk controller unit. The plurality of disk drives has different communication interfaces and connected to the disk controller unit to communicate with the disk controller unit.
    Type: Grant
    Filed: February 14, 2005
    Date of Patent: September 8, 2009
    Assignee: Hitachi, Ltd.
    Inventors: Katsuyoshi Suzuki, Akihisa Hirasawa
  • Method and system for proximity caching in a multiple-core system
    Patent number: 7584327
    Abstract: Embodiments of the invention relate to a method and system for caching data in a multiple-core system with shared cache. According to the embodiments, data used by the cores may be classified as being of one of predetermined types. The classification may enable efficiencies to be realized by performing different types of handling corresponding to different data types. For example, data classified as likely to be re-used may be stored in a shared cache, in a region of the shared cache that is closest to a core using the data. By storing the data this way, access time and energy consumption may be reduced if the data is subsequently retrieved for use by the core.
    Type: Grant
    Filed: December 30, 2005
    Date of Patent: September 1, 2009
    Assignee: Intel Corporation
    Inventors: Yen-Kuang Chen, Christopher J. Hughes
  • Method, apparatus, and a system for efficient context switch
    Patent number: 7584328
    Abstract: A discussion of a local memory with at least a command block section and a cache section that facilitates an efficient interrupt processing. The command-block section is allocated on a per interrupt basis and contains pointers to cache-lines. When an interrupt is recognized an interrupt, the proposal uses the pointers in the command-block to prefetch the corresponding cache-lines from the cache section of the local memory, which it loads into its local cache buffer. Thus, when the CPU recognizes an interrupt, the information for the context-switch is already available in cache.
    Type: Grant
    Filed: November 14, 2005
    Date of Patent: September 1, 2009
    Assignee: Intel Corporation
    Inventors: Peter C. Brink, Shrikant M. Shah, Peter R. Munguia
  • Methods and arrangements for hybrid data storage
    Patent number: 7584335
    Abstract: Embodiments may comprise a hybrid memory controller to facilitate accesses of more than on type of memory device, referred to generally hereafter as a hybrid memory device or hybrid cache device. The hybrid memory controller may include split logic to determine whether to split data of a write request into more than one portion and to store each portion in a different type of data storage device. For example, one embodiment comprises a hybrid memory controller to store data in both SRAM and DRAM devices. The SRAM and DRAM devices may include distinct circuits on a die, distinct dies within a chip, distinct chips on a memory module, distinct memory modules, or the like.
    Type: Grant
    Filed: November 2, 2006
    Date of Patent: September 1, 2009
    Assignee: International Business Machines Corporation
    Inventor: Scott L. Daniels
  • Mechanism for efficiently processing deferred order-dependent memory access transactions in a pipelined system
    Patent number: RE40921
    Abstract: A bus agent defers an ordered transaction if the transaction cannot be completed in order. When an ordered transaction is deferred, its visibility for the next ordered transaction is asserted if it can guarantee a sequential order of the ordered transaction and the next ordered transaction. This visibility indication allows the bus agent to proceed with the next ordered transaction without waiting for the completion status of the deferred transaction. The visibility indication provides fast processing of ordered transactions.
    Type: Grant
    Filed: October 4, 2001
    Date of Patent: September 22, 2009
    Assignee: Intel Corporation
    Inventors: William S. Wu, Peter D. MacWilliams, Stephen Pawlowski, Muthurajan Jayakumar