Abstract: A method of testing a memory is provided that includes initiating a test on a computer readable memory. The computer readable memory provides output data associated with the test. Further, the method includes selecting to receive the output data from a first register or a second register. In a particular embodiment, the method may include selecting to receive the output data from the first register or the second register by use of a control line. In another particular embodiment, the method may include selecting to receive the RAM input data from the first register or the second register by use of a control line. The control line is configured dynamically by hardware or software on cycle by cycle basis. In a particular embodiment, the test is a built-in-self-test (BIST).

Abstract: A system and method to operate an electronic device, such as a memory chip, in a test mode using the device's built-in ODT (on die termination) circuit is disclosed. One or more test mode related signals, which include on-die signals and other relevant information, may be transferred from the integrated circuit of the electronic device to an external processor using the device's ODT circuit instead of the output data signal driver circuit. Therefore, no capacitive loading of output drivers occurs during test mode operations. Thus the speed of the output data path (i.e., the circuit path propagating non-test mode related signals from the electronic device to other external units in the system) is not affected by test mode operations, allowing a system designer to increase the speed of the data output path as much as desired. Further, deterioration in the quality of signals output from the output drivers is also avoided.

Abstract: A method and system for testing a high-speed circuit is disclosed. The method and system include obtaining a high-speed statistical signature of the high-speed circuit using a conventional tester. The method and system further include comparing the high-speed statistical signature of the high-speed circuit to an expected signature. Consequently, it can be determined whether the high-speed circuit functions within the desired parameters.

Abstract: The concept of applying fencing logic to Built-In Self Test (BIST) hardware structures for the purpose of segregating defective circuitry and utilizing the remaining good circuitry is a well known practice in the chip design industry. Described herein is a method for verifying that any particular implementation of partial fencing logic actually provides the desired behavior of blocking down-stream impact of all signals from fenced interfaces, and also ensuring that the partial fencing does not inadvertently preclude any common logic from being fully tested.

Abstract: A method and system for enterprise memory management of memory modules of a computer system. The method includes scanning memory chips of a memory module for errors, analyzing a scrub error map corresponding to a scrubbing operation of the memory module, generating a scrub map summary based upon the scrub error map analyzed, creating an error history map by adding the scrub map summary generated, analyzing the error history map created and tracking a chip location for each memory chip of the memory module including errors, and determining a scrubbing algorithm of the memory module based on the analyzed error history map. The enterprise memory management system includes a plurality of computers each including memory modules, and an enterprise memory manager which collects and analyzes error history maps corresponding to each computer and determines a scrubbing algorithm of the memory modules of each computer.

Abstract: A test apparatus includes a pattern memory for storing a test pattern to be inputted to a memory-under-test, an address generating section for sequentially outputting addresses of the memory-under-test into which the test pattern is to be written, a pointer section for sequentially pointing each address of the pattern memory to cause the pattern memory to output the test pattern in synchronism with the address of the memory-under-test outputted out of the address generating section, a bad block memory for storing an address of a bad block of the memory-under-test in advance and a pointer control section for causing the address generating section to output a next address of the memory-under-test while holding the address of the pattern memory outputted out of the pointer section when the address of the memory-under-test generated by the address generating section coincides with any one of addresses stored in the bad block memory.

Abstract: An integrated circuit including embedded test functionality. An integrated circuit may include a plurality of processor cores each configured to execute instructions, and a test access port configured to interface circuits included within the integrated circuit with a test environment external to the integrated circuit for testing of the circuits. The test access port may include virtualization logic configured to allow a first set of instructions executing on the given processor core to control activity of the test access port for testing of the circuits. In one embodiment, the circuits may be accessible for testing via a plurality of scan chains, wherein the scan chains and the test access port are compliant with a version of Joint Test Access Group (JTAG) standard IEEE 1149, and wherein the test access port includes a Test Data In (TDI) pin, a Test Data Out (TDO) pin, and a Test Clock (TCK) pin.

Abstract: There is provided a test apparatus that tests a device under test.

Abstract: A random number test circuit includes a counting unit to count number of repetitions of a certain-value bit in a random number sequence, the repetitions occurring in series, a detecting unit to detect a plurality of numbers corresponding to a kind of bits in the random number sequence, and a determining unit to determine whether the random number sequence is normal, based on the numbers.

Abstract: A master and a slave stage of a flip-flop are each separately clocked with non-overlapping clock signals during scan mode to eliminate a data input scan mode multiplexer. Separate, non-overlapping clocking permits the elimination of hold violations in scan mode for scan mode flip flop chains, permitting the elimination of delay buffers in the scan mode data paths. Resulting application circuits have reduced circuit area, power consumption and noise generation. A clock generator for scan mode clocking is provided to obtain the separate, non-overlapping scan mode clocks. Scan mode clocks may be generated with a toggle flip flop, a pulse generator or a clock gating circuit.

Abstract: Aspects of a method and system of using a single EJTAG interface for multiple TAP controllers may comprise communicating information to a plurality of debugging interfaces, the method comprising simultaneously broadcasting a single debug message to a plurality of TAP controllers where the debug message is received via a single debug interface. The method may further comprise simultaneously broadcasting the single debug message to selected ones of a plurality of TAP controllers. An input enable register control signal may be generated that selects which, of a plurality of TAP controllers, is to receive the debug message. The single debug interface may be a JTAG interface which is capable of receiving and sending JTAG messages, or EJTAG messages.

Abstract: A test system is disclosed wherein a device under test (DUT) includes a trace logic analyzer (TLA) that receives and stores test data. The test system includes both a master tester and a slave tester. The slave tester operates at a high speed data rate substantially faster than that of the master tester. The master tester instructs the TLA to monitor data that the DUT receives from the slave tester to detect a predetermined data pattern within the data. The slave tester transmits data including the predetermined data pattern to the DUT. The DUT receives the data. When the TLA in the DUT detects the predetermined data pattern in the received data, the TLA stores that data pattern as a stored data pattern. The master tester retrieves the stored data pattern and compares the stored data pattern with the original predetermined data pattern. If the master tester determines that the stored data pattern is the same as the original predetermined data pattern, then the master tester generates a pass result.

Abstract: A physical coding sublayer (PCS) device includes a first data scrambler, a second data scrambler, and a selector. The first data scrambler scrambles first data and implements a first scrambling cycle. The second data scrambler scrambles second data and implements a second scrambling cycle. The second data is different than the first data. The second scrambling cycle is shorter than the first scrambling cycle. The selector selects the first data scrambler to scramble the first data during normal operations. The selector selects the second data scrambler to scramble the second data during testing. The first data scrambler does not scramble the second data. The second data scrambler does not scramble the first data.

Abstract: A device is provided for detecting temperature-induced delays in a combinational logic path. A signal at the output of the logic path is latched at a first latch using a primary clock signal. The primary clock signal is delayed by a delay element to provide a delayed clock signal. The output of the logic path is latched at a second latch using the delayed clock signal. The delay element delays the clock signal by an amount that indicates the occurrence of an over-temperature condition at the logic path. A comparator compares the data latched at the first latch to the data latched at the second latch and provides an error signal indicative of an over-temperature condition if the first and second latch contain different data values.

Abstract: A method for performing a test of a high-speed integrated circuit with at least one functional unit and built-in self-test features by a low-speed test system. The method comprises the steps of transforming an external clock signal from the test system into a faster internal clock signal within the integrated circuit, generating a test pattern according to a predetermined scheme, and applying the test pattern to the functional unit, comparing a response from the functional unit with an expected test pattern. If the response differs from the expected test pattern, then an internal failure signal is generated and the internal failure signal is extended to a length, which may be recognized by the test system. Further the present invention relates to a high-speed integrated circuit with at least one functional unit and built-in self-test features.

Abstract: An apparatus for locating a defect in a scan chain by recording the last bit position in a serial data stream at which a certain data state is observed during a test comprising a plurality of patterns.

Abstract: A method and apparatus for testing an integrated circuit using built-in self-test (BIST) techniques is described. In one aspect, a BIST circuit comprises a scan monitor with hold logic and a signature generation element. The hold logic is operable to suspend signature generation in the signature generation element at any desired point in the test sequence. In some embodiments, the hold logic comprises a scan-loadable signature hold flip-flop which allows the logic BIST controller to be restarted from any selected pattern within a pattern range and to run to any subsequent pattern. The BIST session can be run incrementally, testing and reporting intermediate MISR signatures. External automatic testing equipment can suspend signature generation at selected times during a BIST session to prevent tainting of the signature generation element. The hold logic also may comprise a rotating hold ring to suspend signature generation during predetermined shift cycles.

Abstract: Disclosed is a technique for updating a read-detect channel. A signal is processed in a read-detect channel that has one or more programmable registers. While signals continue to be processed by the read-detect channel, it is determined with a channel auxiliary processor whether to dynamically replace values of the one or more programmable registers. When it is determined that values of the one or more programmable registers are to be replaced, a channel auxiliary processor determines values for the one or more programmable registers and replaces existing values for the one or more programmable registers with the determined values.

Abstract: An electronic element, test system and method of testing an electronic circuit are provided. The electronic circuit has input and output terminals. The input terminals receive a test signal sequence to test the electronic circuit. Actual value signals of a 3-value logic of the electronic circuit are provided at the output terminals in response to the test signal sequence. A comparator circuit has first and second input terminals and an output terminal. Each of the output terminals of the electronic circuit are coupled to a first input terminal. The second input terminals receive desired value signals. The comparator circuit compares the actual value signals with the desired value signals and provides the comparison to the output terminal of the comparator circuit.

Abstract: In some embodiments, a method for testing a memory having a plurality of bits is provided and includes initializing each value in a first register to zero. Next, each value in a second register is initialized to one. Further, each bit in the memory is initialized to zero. A logical OR operation is applied to each bit in the memory with a bit value as the first operand and a corresponding register value in the first register as the second operand. Additionally, the method includes initializing each bit in the memory to one. Also, a logical AND operation is applied to each bit in the memory with the bit value as the first operand and a corresponding register value as the second operand.