Abstract: A processor includes a multi-level cache hierarchy where locality information property such as a Low Locality of Reference (LLR) property is associated with a cache line. The LLR cache line retains the locality information and may move back and forth within the cache hierarchy until evicted from the outer-most level of the cache hierarchy.

Abstract: Provided are methods for borrow processing in storage pools. A plurality of physical volumes are allocated to a first storage pool. A determination is made whether the first storage pool has less than a threshold number of empty physical volumes. If the first storage pool has less than the threshold number of empty physical volumes, then at least one empty physical volume is borrowed to the first storage pool from a second storage pool.

Abstract: A mixed serial-parallel content addressable memory (CAM) includes serial CAM cells and parallel CAM cells that are arranged in multiple (N) columns and multiple (M) rows. Each row includes at least one serial CAM cell and at least two parallel CAM cells. The M rows are searched in parallel. For each row, the serial CAM cells are searched sequentially, and the parallel CAM cells are selectively searched in parallel. The CAM further includes a driver that generates search lines for the N columns of CAM cells, one search line per column. The driver sets the search lines to an N-bit value to search for in the CAM. Prior to each search operation, the driver presets at least one search line for at least one column of serial CAM cells to precharge a match line for each row.

Abstract: A memory controller for controlling a daisy chain of self timed memory chips. The memory controller has information as to how long each self timed memory chip in the daisy chain of memory chips takes to make a read access and a write access to an array on the self timed memory chip. The memory controller determines current access time information on a memory chip by sending a command to the memory chip. The memory chip returns a data word containing the current access time information. Alternatively, the memory controller transmits an address/command word to the memory chip and, after completing an access, transmits a responsive data word to the memory controller. The memory controller determines the access time information using the interval from transmission of the address/command word to reception of the responsive data word.

Abstract: A cache coherent data processing system includes at least first and second coherency domains. The first coherency domain includes a system memory controller for a system memory and a first processing unit having a first cache memory. The second coherency domain includes a second processing unit having a second cache memory. In the first cache memory, a coherency state field associated with a storage location and an address tag is set to a first coherency state. In response to snooping an exclusive access request specifying a target address matching the address tag, the first cache memory provides a first partial response to the exclusive access request based at least in part upon the first coherency state. In response to snooping the exclusive access request, the memory controller determines whether it is responsible for the target address and provides a second partial response to the exclusive access request based at least in part upon an outcome of the determination.

Abstract: A problem with a journaling file system is that the load on input/output processing executed between a server and a storage system is increased because a journal log is written when the file system is updated and updated data is written when flush processing is executed. In a system according to the present invention, a storage system that has received journal logs from a server uses updated data included in the journal logs to execute flush processing.

Abstract: A control arrangement, for example, in a digital component that forms part of a system, draws an input current for its operation and is configured for monitoring an interface for any one of a group of commands and, upon detecting an issued one of the group of commands, operates the component for executing the issued command in an operational mode, and during an idle time on the interface, the control arrangement exclusively monitors the interface for any one of the group of commands such that the input current is limited to a leakage current. The component may draw less than 1 milliamp of current during the idle mode.

Abstract: A method, system, and computer program product are provided to synchronize data maintained in separate storage areas using a copy-on-read technique. The separate storage areas may be distributed across a network, and the replicas of the data may be used for backup and/or disaster recovery purposes. Storage objects containing data and information relevant to managing the data by a particular application are identified, and only those storage objects are read. Data contained in the storage objects read are then copied to the replica storage area. This process avoids reading non-useful data, making the synchronization more efficient and conserving bandwidth of connections over which the data are sent.

Abstract: A computer implemented method, data processing system, and computer program product for reducing memory traffic via detection and tracking of temporally silent stores. When a memory store, comprising an address and a data value, to a cache is detected, a determination is made that a cache line in the cache contains a same address as the address in the memory store. A determination is then made that a tentative cache line invalidate signal for the cache line was previously sent to other data processing systems in the network to tentatively invalidate the cache line. If the memory store is a temporally silent store, a cache line revalidate signal is sent to the other data processing systems to clear the tentative invalidate signal for the cache line.

Abstract: Methods and arrangements to insert values in hash tables are contemplated. Embodiments include transformations, code, state machines or other logic to insert values in a hash table stored in electronic memory by hashing a value to determine a home address of an entry in the hash table, the hash table having a plurality of entries, each entry comprising an address, a value, and a link. The embodiments may include determining whether there is a collision of the value with a value stored in the entry; inserting the value in the entry if there is no collision; and generating the addresses of further entries until an entry is found in which the value can be inserted if there is a collision. The embodiments may include generating a plurality of addresses of entries based upon the address of a previously generated entry.

Abstract: Disclosed is a method of performing a read operation in a NAND/RAM semiconductor memory device. The semiconductor memory device comprises a NAND flash memory device having a memory cell array and a page buffer, and a data RAM outputting data in response to a clock signal received from a host. The method comprising; sensing data stored in one page of the memory cell array in the page buffer, transferring the sensed data from the page buffer to the data RAM in multiple blocks via a corresponding number of transfer operations, and reading the transferred data from the data RAM in response to the host clock signal, wherein a read-out operation for the transferred data commences during any one of the plurality of transfer time periods.

Abstract: A flash real time operating system for embedded applications employing flash memory is capable of storing and accessing individual bytes of data corresponding to a particular logical address in real time. The operating system writes data bytes to sequential physical blocks within the flash memory. Physical blocks written with data bytes corresponding to the same logical address are connected by a linked list, which is dynamically modified to reduce access times required to read and write data to the flash memory. The operating system also monitors the number of physical blocks written with data within each physical sector. When one physical sector reaches its storage capacity, the operating system transfers the physical blocks holding valid data from the old physical sector to a new, previously erased physical sector.

Abstract: An information processing apparatus, including: a file memory to store data; a file controller to access the file memory; a first control section to manage the file memory via the file controller; and a second control section connected with the file controller; wherein the file controller includes an usage information management section to manage information representing un-use condition in each divided region of the file memory, and wherein the information processing apparatus further includes a data storing control section to store data in the file memory from the second control section via the file controller by referring the information when the first control section is in un-operative condition.

Abstract: A system and method of managing stored data in a storage management system. The storage management system includes a storage manager, a media agent connected to the storage manager, and a primary volume connected to the media agent. A plurality of snapshots are taken of the primary volume. The snapshots are indexed by associating respective information with the snapshot. The indexed snapshots are copied to a recovery volume. In this way, browsing features are enabled for the user. The user may view the snapshots in a hierarchical format, and may even view snapshot data in association with the corresponding application. The resultant recovery volume may be used to replace a primary volume.

Abstract: A disk drive that includes nonvolatile memory for use when the disk drive is in standby mode also uses the nonvolatile memory, together with a volatile memory, as a cache when the disk drive is in both standby and non-standby mode. Each of the data blocks stored on the disks is also stored in a cache line of either the volatile memory or the nonvolatile memory. Each cache line in both the volatile and nonvolatile memory stores one or more data blocks and an associated tag. The tag contains at least a portion of the logical block address that corresponds to the data block that is stored in the cache line. The volatile memory also has locations allocated to store tags that “shadow” the tags in the nonvolatile memory. By searching the shadow tags in the faster volatile memory, it can be determined if a data block is in the nonvolatile memory without searching the slower nonvolatile memory.

Abstract: A fixed number of variable-length instructions are stored in each line of an instruction cache. The variable-length instructions are aligned along predetermined boundaries. Since the length of each instruction in the line, and hence the span of memory the instructions occupy, is not known, the address of the next following instruction is calculated and stored with the cache line. Ascertaining the instruction boundaries, aligning the instructions, and calculating the next fetch address are performed in a predecoder prior to placing the instructions in the cache.

Abstract: This storage controller providing a volume for storing data transmitted from a host system includes a management unit for managing the data written in the volume with a first block area, or a second block area in the first block area which is smaller than the first block area; a snapshot acquisition unit for acquiring a snapshot of the volume at a prescribed timing; and a transfer unit for transferring the data of the volume acquired with the snapshot of the snapshot acquisition unit to an external device with the first block area or the second block area.

Abstract: A management computer includes a management unit for managing the load of the virtual storage extent and the threshold value thereof in the virtual storage subsystems for each prescribed period; and a migration command unit for commanding, when the load of the virtual storage extent managed by the management unit exceeds the threshold value and with the virtual storage extent as the virtual storage extent to be migrated, the migration of the virtual storage extent to be migrated to another virtual storage subsystem that is mutually communicable with a host computer provided with the virtual storage extent to be migrated and a storage subsystem having the storage extent associated with the virtual storage extent to be migrated; and wherein the virtual storage subsystem includes a migration unit for migrating the virtual storage extent to be migrated commanded by the migration command unit to the other virtual storage subsystem.

Abstract: The present invention extends to methods, systems, and computer program products for identifying relevant information to cache. A computer system accesses a marked data entity that has been marked for caching at a client computer system. The marked data entry is marked for caching based on the relevance of the marked data entity from the perspective of a requested data entity. The computer system identifies relationships from the marked data entity to one or more other data entities. The computer system selects, from among the identified relationships, any relationships that satisfy a relevance threshold from the perspective of the requested data entity. The computer system identifies, from among the one or more other data entities, any of the other data entities that correspond to a selected relationship satisfying the relevance threshold. The computer system marks the identified other data entities for caching.

Abstract: The present invention provides a memory device of a type that outputs a ready signal to the outside, and that is capable of achieving an enhanced data transfer rate and a uniform latency time. A memory device according to the present invention includes a ready signal sending portion, and the ready signal sending portion monitors a memory portion to detect the memory portion becoming ready for reading or writing of specified data. The ready signal sending portion generates a first ready signal that changes from a busy state to a ready state after the detection and an enabling signal that changes from a disable state to an enable state on the basis of a preset ready generating timing value. When the first ready signal is in the ready state and the enabling signal is in the enable state, the ready signal sending portion sends to the outside a second ready signal that is in a ready state.