Abstract: A storage subsystem includes a controller having a plurality of ports and a plurality of storage devices configured store information. A lock table includes attribute information and retention information for each of a plurality of storage volumes presented to a host device. The plurality of storage volumes includes a non-virtual volume that maps to a first storage device of the storage subsystem and a virtual volume that maps to a second storage device of an associated storage subsystem. The associated subsystem is linked to the storage subsystem via a communication link. The controller is configured to receive and process a request from a host to modify an attribute of the virtual volume.

Abstract: Systems, apparatuses and methods for controlling access operations in a memory device that may include a memory controller(s) and memory. Commands, registers and/or other mechanisms may be defined to be supported by the memory device, where such commands, registers, and/or other mechanisms facilitate the control of read and write/erase operations to allow these operations to be performed simultaneously. Thus, a write and/or erase operation may be initiated on a first memory, a read operation initiated by a set of commands on a second memory, wherein the read and write/erase operations are performed substantially at the same time.

Abstract: To make content irreproducible in a recording device after a set expiration time, the recording device has a read/write unit for reading and writing data on a recording unit, the read/write unit having electric power supplied from an external power source, a clock containing a built-in battery, an input/output interface for inputting data from outside and outputting data to outside, and a controller for controlling the read/write unit and the input/output interface. The recording medium includes an ordinary data area for writing ordinary data and an expiration time data area for writing an expiration time of ordinary data. The controller prevents ordinary data written in the ordinary data area from being output to outside when the expiration time written in the expiration time area has passed a time limit calculated by the clock.

Abstract: In one embodiment of the present invention, a method includes switching between a first address space and a second address space, determining if the second address space exists in a list of address spaces; and maintaining entries of the first address space in a translation buffer after the switching. In such manner, overhead associated with such a context switch may be reduced.

Abstract: Proposed are a storage system, data processing method and storage apparatus capable of performing stable data I/O processing. Each of the storage apparatuses configured in the storage group stores group configuration information containing priority information given to each storage apparatus, and the storage apparatus with the highest priority becomes a master and performs virtualization processing and data I/O processing, and another storage apparatus belonging to this storage group performs internal processing of the storage group.

Abstract: A disk array device having a plurality of hard disk units has a large-capacity memory mounted on a controller module which controls the whole device. The large-capacity memory has a system area managed by an OS and a cache area serving as a cache memory, and in addition, it has a table area which stores management/control information of the device and whose area size is changeable at an arbitrary instance. Therefore, it is possible to change the table area according to the state of the device in an active state without ON/OFF of a power source, so that an area not in use in the table area can be released for use as the cache memory. This makes it possible to appropriately varying the sizes of the table area and the cache area in an active state while the device is in operation, thereby realizing effective use of the large-capacity memory.

Abstract: Methods and apparatus are provided for selectively replicating a data structure in a low-latency memory. The memory includes multiple individual memory banks configured to store replicated copies of the same data structure. Upon receiving a request to access the stored data structure, a low-latency memory access controller selects one of the memory banks, then accesses the stored data from the selected memory bank. Selection of a memory bank can be accomplished using a thermometer technique comparing the relative availability of the different memory banks. Exemplary data structures that benefit from the resulting efficiencies include deterministic finite automata (DFA) graphs and other data structures that are loaded (i.e., read) more often than they are stored (i.e., written).

Abstract: A data processing system having debugging circuitry and a method for operating the data processing system is provided. In the system, a processor has a cache memory and is coupled to a system bus. An instruction is received which indicates an effective address. The instruction is executed and it is determined if the effective address results in a hit or a miss in the cache. If the effective address results in a hit, data associated with the effective address is provided from the cache to the system bus without modifying a state of the cache. The instruction allows real-time debugging circuits to be able to view the current value of one or more variables in memory that may be hidden from access due to cache hierarchy without modifying the value or impacting the current state of the cache.

Abstract: Methods for a treatment of cached objects are described. In one embodiment, management of a region of a cache is configured with an eviction policy plug-in. The eviction policy plug-in includes an eviction timing component and a sorting component, with the eviction timing component including code to implement an eviction timing method, and the eviction timing method to trigger eviction of an object from the region of cache. The sorting component includes code to implement a sorting method to identify an object that is eligible for eviction from said region of cache. The sorting method includes identifying an object for eviction that is cached in the region of cache and that has been used less frequently than other objects that are cached in the region of cache.

Abstract: System, method and program for managing a storage server comprising first and second clusters of storage controllers. The first cluster comprises one or more storage controllers each controlling one or more storage arrays. The first cluster also comprises a first cache memory and a first nonvolatile storage (“NVS”) shared by the one or more storage controllers of the first cluster. The second cluster comprises one or more storage controllers each controlling one or more storage arrays. The second cluster also comprises a second cache memory and a second nonvolatile storage shared by the one or more storage controllers of the second cluster. There is monitoring of an amount of time that data controlled by each of the clusters is held in the cache memory of the cluster before being outpaged to the storage arrays. There is monitoring of an amount of requests to access storage arrays of a cluster that were delayed due to insufficient NVS.

Abstract: Methods, apparatus and software products are described for design-time data-assignment techniques for hierarchical memories, e.g., multi-banked memories in an essentially digital system as well as methods, apparatus and software products for run-time memory management techniques of such a system. Memory assignment techniques are described for assigning data to a hierarchical memory particularly for multi-tasked applications where data of dynamically created/deleted tasks is allocated at run-time. The energy consumption of hierarchical memories such as multi-banked memories depends largely on how data is assigned to the memory banks. Methods, apparatus and software products are described for design-time data-assignment techniques for hierarchical memories, e.g., multi-banked memories in an essentially digital system which improve a cost function such as energy consumption.

Abstract: Dynamically allocated memory is managed in real-time. This real-time management capability enables an invalid access of the dynamically allocated memory to be detected at the time the invalid access occurs, rather than at some later point in time. This real-time management capability can be dynamically activated/deactivated on a per process basis.

Abstract: A method, system, and program for managing memory page requests in a multi-processor data processing system determines a threshold value of available memory, and dynamically adjusts an allocation time to fulfill a page request if the available memory is below a threshold value. The allocation time to fulfill the page request is based upon a percentage of available memory pages once a page stealer commences a scan for pages. An allocation wait time is inversely proportionally adjusted depending upon the percentage of available memory. The allocation wait time has a duration that increases in time as the percentage of available memory decreases and decreases in time as the percentage of available memory increases. More specifically, an average time per page to allocate a page including a scan time for the scan in computing the average time is determined. Then a tunable value is applied to the average time to determine a wait time.

Abstract: A memory circuit having a plurality of memory areas, whose order depends on respectively associated logical addresses, and which each have an associated control value, and a control means, which is designed such that the same assigns a value to a control value associated with a target memory area when writing into the same, which corresponds to the value of a lowest used memory area, when one exists, and assigns the same an arbitrary or predetermined value, when none exists, and when a predetermined condition is fulfilled, and when at least two used memory areas exist, rewrites the content of a next memory area, whose control value has a predetermined relation to the control value of the lowest memory area, and changes the control value of this memory area, when the same exists, or rewrites a content of the lowest memory area and changes the associated control value, when the next memory area, whose control value has a predetermined relation to the control value of the lowest memory area, does not exist.

Abstract: A computer system memory is structured as contiguous memory chunks, each chunk having a header. A chunk header includes a first offset value, a sign bit associated with the first offset value, and a number of bits having values that are added to a second offset value that is determined from the first offset value. In particular, the actual offset value can be determined by adding the values of the bits to the second offset value and by multiplying the result by the binary equivalent of four. The second offset value is then used for determining an actual offset value that is applied to a base address to provide a memory location of the memory chunk.

Abstract: Bit inversions occurring in memory systems and apparatus are provided. Data is acquired from a source destined for a target. As the data is acquired from the source, the set bits associated with data are tabulated. If the total number of set bits exceeds more than half of the total bits, then an inversion flag is set. When the data is transferred to the target, the bits are inverted during the transfer if the inversion flag is set.

Abstract: A method for protecting memory is provided. The method includes reading a block of data from a storage drive and writing the block of data to a first memory portion and a second memory portion. The method also includes managing the first memory portion and the second memory portion to protect the block of data. The block of data can be recovered from a non-failing portion in case either the first memory portion or the second memory portion fails.

Abstract: An integrated circuit comprising a plurality of processor cores operable to perform respective data processing operations, at least one of said processor cores being configurable to operate either in a coherent multi-processing mode having access to a coherent region within a memory shared with at least one other processor core or in a non-coherent mode.

Abstract: This invention is a system and method for backup and recovery of data using a new architecture that includes continuous backup and information protection backup and recovery system components.

Abstract: Avoiding cache-line sharing in virtual machines can be implemented in a system running a host and multiple guest operating systems. The host facilitates hardware access by a guest operating system and oversees memory access by the guest. Because cache lines are associated with memory pages that are spaced at regular intervals, the host can direct guest memory access to only select memory pages, and thereby restrict guest cache use to one or more cache lines. Other guests can be restricted to different cache lines by directing memory access to a separate set of memory pages.