Patents Examined by Kevin L. Ellis
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Patent number: 8006063Abstract: It is made possible to update information registered in a database of iSNS, SLP and the like in response to a configurational change in a storage device, and for a host computer to discover a disk volume. In response to changes in contents of operation to alter a storage configuration such as in creating or deleting a volume or LUN, contents of the alteration are reflected in the database of iSNS or SLP. Also, in response to a change in setting of LUN masking, a discovery domain of iSNS or attribute values of SLP are updated so that the host computer can discover the disk volume. Also, objects and services are reregistered periodically according to a registration period of iSNS or lifetime of SLP to prevent registered contents from expiring.Type: GrantFiled: September 22, 2009Date of Patent: August 23, 2011Assignee: Hitachi, Ltd.Inventors: Yasuyuki Mimatsu, Masayuki Yamamoto
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Patent number: 8001343Abstract: To provide a power controlling method for use in a storage device which can be operated with less power consumption, at least a storage capacity monitoring unit for monitoring the storage amount of data stored in each storage unit, a power-on unit for controlling the power-on of each storage unit, an access state monitoring unit for monitoring the state of accesses from an upper device to each storage unit, and a power-off unit for controlling the power-off of each storage unit are comprised, thereby controlling the power of a second storage unit.Type: GrantFiled: June 6, 2006Date of Patent: August 16, 2011Assignee: Fujitsu LimitedInventor: Kunihiko Kassai
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Patent number: 8001317Abstract: A data writing method for a non-volatile memory is provided, wherein the non-volatile memory includes a data area and a spare area. In the data writing method, a plurality of blocks in a substitution area of the non-volatile memory is respectively used for substituting a plurality of blocks in the data area, wherein data to be written into the blocks in the data area is written into the blocks in the substitution area, and the blocks in the substitution area are selected from the spare area of the non-volatile memory. A plurality of temporary blocks of the non-volatile memory is used as a temporary area of the blocks in the substitution area, wherein the temporary area is used for temporarily storing the data to be written into the blocks in the substitution area.Type: GrantFiled: February 4, 2008Date of Patent: August 16, 2011Assignee: Phison Electronics Corp.Inventors: Chih-Kang Yeh, Chien-Hua Chu, Jia-Yi Fu
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Patent number: 7996630Abstract: Provided is a method of managing memory in a multiprocessor system on chip (MPSoC). According to an aspect of the present invention, locality of memory can be reflected and restricted memory resources can be efficiently used by determining a storage location of a variable or a function which corresponds to a symbol with reference to a symbol table based on memory access frequency of the variable or the function, comparing the determined storage location and a previous storage location, and copying the variable or the function stored in the previous storage location to the determined storage location if the determined storage location is different from the previous storage location.Type: GrantFiled: August 11, 2010Date of Patent: August 9, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Keun Soo Yim, Jeong-joon Yoo, Young-sam Shin, Seung-won Lee, Han-cheol Kim, Jae-don Lee, Min-kyu Jeong
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Patent number: 7996620Abstract: A cache memory high performance pseudo dynamic address compare path divides the address into two or more address segments. Each segment is separately compared in a comparator comprised of static logic elements. The output of each of these static comparators is then combined in a dynamic logic circuit to generate a dynamic late select output.Type: GrantFiled: September 5, 2007Date of Patent: August 9, 2011Assignee: International Business Machines CorporationInventors: Yuen H. Chan, Ann H. Chen, Kenneth M. Lo, Shie-ei Wang
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Patent number: 7996598Abstract: A methodology for efficiently copying data is presented. An internal controller RAM is multiplexed between storing existing RAM data such as look up table data) and storing copy back data with respect to a flash memory. The data in the controller RAM is temporarily stored in a free space of the flash memory. The data of the flash memory, which is to be copied, is read from a source page and is stored in the free space of the controller RAM, and from there, the data is written to a destination block of the flash memory. After completion of the copy back operation, the data of the controller RAM that was moved to the free space is retrieved for storage back in the controller RAM.Type: GrantFiled: March 14, 2007Date of Patent: August 9, 2011Assignees: STMicroelectronics Pvt. Ltd., STMicroelectronics S.A.Inventors: Alok Kumar Mittal, Chander Bhushan Goel, Hubert Rousseau
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Patent number: 7996608Abstract: A system, method, apparatus, and computer-readable medium are described for providing redundancy in a storage system. According to one method, maps are generated and stored that define stripe patterns for storing data on the storage nodes of a storage cluster. The maps are defined such that when a new storage node is added to the cluster, no movement of data occurs between two storage nodes that existed in the cluster prior to the addition of the new storage node during re-striping, and such that the data stored on each storage node is mirrored on another storage node. Storage nodes may also be designated as an owner or a peer for each storage zone. Input/output operations received at an owner node are fielded directly and mirrored to the peer node, while input/output operations received at a peer node are redirected to the owner node for processing.Type: GrantFiled: October 20, 2006Date of Patent: August 9, 2011Assignee: American Megatrends, Inc.Inventors: Paresh Chatterjee, Ajit Narayanan, Narayanan Balakrishnan, Vijayarankan Muthirisavenugopal
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Patent number: 7991950Abstract: A method and apparatus for incremental package deployment are described. In one embodiment, the method includes the redirection of disk input/output (I/O) requests to preserve contents of disk memory. Following redirection of the disk I/O request, a software distribution package is created according to disk I/O write requests redirected to unused blocks of disk memory. In one embodiment, the software distribution package is generated using a firmware agent, which uploads the software distribution package to a server, which provisions the software distribution packet to other computers within a uniform environment to ensure that each system within the uniform environment has an identical system and memory image. Other embodiments are described and claimed.Type: GrantFiled: June 12, 2009Date of Patent: August 2, 2011Assignee: Intel CorporationInventors: Cong Li, Jun J. Wang, Jianfeng Mei
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Patent number: 7991966Abstract: This disclosure presents an architectural mechanism which allows a caching bridge to efficiently store data either inclusively or exclusively based upon information configured by an application. An INC bit is set for each access to a page table that indicates whether the data is shared or not shared by a LLC. This allows a multicore multiprocessor system to have a caching policy which enables use of the last level cache efficiently and results in improved performance of the multicore multiprocessor system.Type: GrantFiled: December 29, 2004Date of Patent: August 2, 2011Assignee: Intel CorporationInventor: Krishnakanth V. Sistla
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Patent number: 7987329Abstract: A storage system is utilized to its fullest storage capacity by setting a write inhibitive attribute to a desired storage area of the storage system. The storage system has a logical volume in which data is stored and a control device which controls access to the data stored in the logical volume. A first area of a desired size is set in the logical volume, and an access control attribute is set to the first area. In response to a request made by a computer to perform access to the logical volume, the control device notifies the computer that the control device does not perform the access when an area designated by the access request contains at least a part of the first area and the access control attribute set to the first area inhibits the type of the access requested.Type: GrantFiled: December 2, 2008Date of Patent: July 26, 2011Assignee: Hitachi, Ltd.Inventors: Shunji Kawamura, Hisao Homma, Yasuyuki Nagasoe
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Patent number: 7987324Abstract: Provided is an apparatus and method for searching update data of an external memory. The apparatus includes the detachable external memory, a data management unit, and a controller. The detachable external memory stores a File Allocation Table (FAT) and a plurality of pieces of data. The data management unit updates a first FAT and creates a second FAT having the same information as the first FAT. The controller controls the data management unit to access the requested data, update information on the first FAT, and create the second FAT.Type: GrantFiled: October 18, 2007Date of Patent: July 26, 2011Assignee: Samsung Electronics Co., LtdInventor: Sung-Chan Lee
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Patent number: 7984230Abstract: There is provided a logical volume management method for storage system. When a logical volume is created on a flash memory drive, a management computer allocates logical volume while flash memory chip border of flash memory drive is taken into account. Specifically, a table for managing a correlation between each parity group and the flash memory chip of the flash memory drive is obtained and the logical volume is allocated in such a manner that a flash memory chip is not shared by a plurality of logical volumes. When complete erasing of logical volume data is performed, the management computer specifies a flash memory chip on which complete data erasing is to be performed, and the storage system completely erases data exclusively on the chip of interest with a use of a function of completely erasing data at a time by chip unit of the flash memory chip (chip erasing).Type: GrantFiled: October 24, 2006Date of Patent: July 19, 2011Assignee: Hitachi, Ltd.Inventors: Hiroshi Nasu, Masayuki Yamamoto, Yuichi Taguchi
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Patent number: 7984241Abstract: A plurality of bits are added to virtual and physical memory addresses to specify the level at which data is stored in a multi-level cache hierarchy. When data is to be written to cache, each cache level determines whether it is permitted to store the data. Storing data at the appropriate cache level addresses the problem of cache thrashing.Type: GrantFiled: July 26, 2006Date of Patent: July 19, 2011Assignee: Hewlett-Packard Development Company, L.P.Inventor: Sudheer Kurichiyath
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Patent number: 7984256Abstract: A data processing system includes a plurality of requestors and a memory controller for a system memory. In response to receiving from the requestor a read-type request targeting a memory block in the system memory, the memory controller protects the memory block from modification, and in response to an indication that the memory controller is responsible for servicing the read-type request, the memory controller transmits the memory block to the requestor. Prior to receipt of the memory block by the requestor, the memory controller ends protection of the memory block from modification, and the requestor begins protection of the memory block from modification. In response to receipt of the memory block, the requestor ends its protection of the memory block from modification.Type: GrantFiled: October 13, 2005Date of Patent: July 19, 2011Assignee: International Business Machines CorporationInventors: James S. Fields, Jr., Guy L. Guthrie, John T. Hollaway, Jr., Derek E. Williams
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Patent number: 7979643Abstract: Embodiments of the present invention provide methods and systems for tuning the size of the cache. In particular, when a page fault occurs, non-resident page data is checked to determine if that page was previously accessed. If the page is found in the non-resident page data, an inter-reference distance for the faulted page is determined and the distance of the oldest resident page is determined. The size of the cache may then be tuned based on comparing the inter-reference distance of the newly faulted page relative to the distance of the oldest resident page.Type: GrantFiled: March 20, 2009Date of Patent: July 12, 2011Assignee: Red Hat, Inc.Inventor: Henri Han van Riel
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Patent number: 7979624Abstract: Various embodiments for performing truncate operations in nonvolatile memory are described. In one embodiment, an apparatus may include a nonvolatile memory to perform one or more truncate operations on a data file written to the nonvolatile memory and a volatile memory to track a truncate operation performed in the nonvolatile memory. Other embodiments are described and claimed.Type: GrantFiled: March 31, 2006Date of Patent: July 12, 2011Assignee: Intel CorporationInventors: Swati Gera, Karey Hart, Neil Gabriel, Lawrence Chang, Patrick McGinty
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Patent number: 7979650Abstract: A method for enhancing computer data backup is disclosed. The method includes storing identifications and corresponding functionalities for a plurality of storage devices in a database. A storage device that is in data communication with a computer that is to be backed up is selected. An identification of the storage device selected for use in the backup is determined. If functionalities for the selected storage device are contained in the database, then at least one of the functionalities for the selected storage device is used to enhance a data backup to the selected storage device if functionalities for the selected storage device are stored in the database. If functionalities for the selected storage device are not contained in the database, then the selected storage device can be queried in an attempt to match it to one of the storage devices contained in the database, so that functionalities for the storage device contained within the database can be used to enhance data backup.Type: GrantFiled: June 13, 2005Date of Patent: July 12, 2011Assignee: Quest Software, Inc.Inventor: Fabrice Helliker
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Patent number: 7979641Abstract: The embodiments of the invention provide a method, apparatus, etc. for a cache arrangement for improving RAID I/O operations. More specifically, a method begins by partitioning a data object into a plurality of data blocks and creating one or more parity data blocks from the data object. Next, the data blocks and the parity data blocks are stored within storage nodes. Following this, the method caches data blocks within a partitioned cache, wherein the partitioned cache includes a plurality of cache partitions. The cache partitions are located within the storage nodes, wherein each cache partition is smaller than the data object. Moreover, the caching within the partitioned cache only caches data blocks in parity storage nodes, wherein the parity storage nodes comprise a parity storage field. Thus, caching within the partitioned cache avoids caching data blocks within storage nodes lacking the parity storage field.Type: GrantFiled: March 31, 2008Date of Patent: July 12, 2011Assignee: International Business Machines CorporationInventors: Dingshan He, Deepak R. Kenchammana-Hosekote
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Patent number: 7979636Abstract: A method of controlling a semiconductor memory card system including a host device incorporating a semiconductor memory card and communicating information with a user of the host device to warn the imminent end of the life of the memory card in the system is provided. According to one aspect, there is provided a method of controlling a semiconductor memory card, the method comprising creating end-of-life index data of the semiconductor memory card, reading the end-of-life index data in response to a command from a host device to the semiconductor memory card, creating an end-of-life warning status of the semiconductor memory card from the end-of-life index data based on a life control limit value, and sending a response containing the end-of-life warning status to the host device as a response to the command through the same communication line as that for the command.Type: GrantFiled: August 13, 2007Date of Patent: July 12, 2011Assignee: Kabushiki Kaisha ToshibaInventor: Takafumi Ito
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Patent number: 7975100Abstract: Provided are a method, system, and article of manufacture, wherein a storage manager application implemented in a first computational device maintains a virtual logical volume that represents a plurality of segments of a linear storage medium of a secondary storage, wherein the virtual logical volume and the plurality of segments are created by the storage manager application. A request for data is received at the first computational device, from a second computational device. The storage manager application moves selected segments of the plurality of segments from the linear storage medium of the secondary storage to a cache storage, in anticipation that the requested data is included in the selected segments that are moved from the linear storage medium of the secondary storage to the cache storage.Type: GrantFiled: August 20, 2007Date of Patent: July 5, 2011Assignee: International Business Machines CorporationInventors: Thomas William Bish, Gregory Tad Kishi, Jonathan Wayne Peake