Abstract: A semiconductor device structure and method for manufacturing the same are provided. The semiconductor device structure includes a first word line, a second word line, a gate dielectric structure, a channel layer, and a bit line. The first word line and second word line extend along a first direction. The gate dielectric structure is disposed on a first sidewall of the first word line and on a second sidewall of the second word line. The channel layer is disposed on a first sidewall of the gate dielectric structure. The bit line is disposed on the channel layer and extends along a second direction substantially perpendicular to the first direction. A first roughness of a first sidewall of the channel is different from a second roughness of a second sidewall of the channel layer.

Abstract: A method for fabricating a semiconductor device includes: forming an etch stopper pad including a sacrificial plug over a substrate and a sacrificial pad over the sacrificial plug; forming an etch target layer over the etch stopper pad; forming a plurality of openings by etching the etch target layer and stopping the etching at the sacrificial pad; forming an air gap by removing the sacrificial pad and the sacrificial plug through the openings; and forming a gap-fill layer that fills the openings and the air gap.

Abstract: A semiconductor device or structure includes a first pattern metal layer disposed between a first supply metal tract and a second supply metal tract, the first pattern metal layer comprising an internal route and a power route. A follow pin couples the first supply metal to the power route. The first supply metal tract comprises a first metal and a follow pin comprises a second metal.

Abstract: Provided herein may be a semiconductor device. The semiconductor device may include a first stacked body including a first stacked insulating layer and a first stacked conductive layer that are alternately stacked; a capacitor plug passing through the first stacked body; and a capacitor multi-layered layer configured to enclose the capacitor plug. The capacitor plug may include metal.

Abstract: A method for fabricating a semiconductor device includes: forming an etch stopper pad including a sacrificial plug over a substrate and a sacrificial pad over the sacrificial plug; forming an etch target layer over the etch stopper pad; forming a plurality of openings by etching the etch target layer and stopping the etching at the sacrificial pad; forming an air gap by removing the sacrificial pad and the sacrificial plug through the openings; and forming a gap-fill layer that fills the openings and the air gap.

Abstract: The present disclosure relates to a resistive random access memory (RRAM) device. In some embodiments, the RRAM device includes a first electrode disposed over a substrate and a second electrode over the first electrode. A doped data storage structure is disposed between the first electrode and the second electrode. The doped data storage structure has a dopant with a doping concentration profile that is asymmetric over a height of the doped data storage structure and that has a maximum dopant concentration at non-zero distances from a top surface and a bottom surface of the doped data storage structure.

Abstract: A semiconductor device has a substrate. A lid is disposed over the substrate. An encapsulant is deposited over the substrate. A film mask is disposed over the encapsulant with the lid exposed from the film mask and encapsulant. A conductive layer is formed over the film mask, encapsulant, and lid. The film mask is removed after forming the conductive layer.

Abstract: A semiconductor structure includes a substrate with a plurality of word line trenches and source/drain regions each adjacent to each word line trench; a word line located in the word line trench, which includes a first conductive layer located at a bottom of the word line trench, a single junction layer and a second conductive layer stacked in sequence, in which a projection of the word line on a sidewall of the word line trench and the projection of the source/drain region on the sidewall of the word line trench have an overlapping region with a preset height, and when a voltage applied to the word line is less than a preset voltage, a resistance of the single junction layer is greater than the preset resistance, to make the first conductive layer and the second conductive layer disconnected.

Abstract: Disclosed are a capacitor for DRAM, a DRAM including the same, and a method of fabricating the same. The DRAM capacitor according to an embodiment may include a first electrode of the DRAM; a second electrode spaced apart from the first electrode; and a dielectric layer including a HfZrO film disposed between the first electrode and the second electrode. The HfZrO film may have an intermediate state corresponding to a phase transition region between a first state in which a tetragonal crystalline phase with anti-ferroelectricity property or a tetragonal crystalline phase is dominant, and a second state in which the orthorhombic crystalline phase with anti-ferroelectricity property or the orthorhombic crystalline phase is dominant. The HfZrO film may include both of the tetragonal crystalline phase and the orthorhombic crystalline phase. The HfZrO film maintains an intermediate state corresponding to the phase transition region within the operating voltage range of the capacitor.

Abstract: Apparatus and circuits including transistors with different polarizations and methods of fabricating the same are disclosed. In one example, a semiconductor structure is disclosed. The semiconductor structure includes: a substrate; an active layer that is formed over the substrate and comprises a first active portion and a second active portion; a first transistor comprising a first source region, a first drain region, and a first gate structure formed over the first active portion and between the first source region and the first drain region; and a second transistor comprising a second source region, a second drain region, and a second gate structure formed over the second active portion and between the second source region and the second drain region, wherein the first active portion has a material composition different from that of the second active portion.

Abstract: The present disclosure provides a semiconductor structure and a forming method thereof, including: providing a substrate and a plurality of discrete bit line structures, the bit line structures being located on the substrate, capacitor contact windows being provided between adjacent bit line structures; forming first isolation layers, the first isolation layers covering sidewalls of the bit line structures; forming a sacrificial layer, the sacrificial layer covering sidewalls of the first isolation layers; forming second isolation layers, the second isolation layers covering sidewalls of the sacrificial layer and exposing the top surfaces and bottoms of the sacrificial layer; etching the exposed bottoms of the sacrificial layer to form bottom gaps between the first isolation layers and the second isolation layers; etching the exposed top surfaces of the sacrificial layer to remove the remaining of the sacrificial layer so as to form gaps between the layers.

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate defining a plurality of trenches; and a plurality of bit line contacts disposed on the substrate, wherein at least one of the plurality of bit line contacts is disposed within one of the trenches defined by the substrate, wherein the plurality of trenches has a first row and a second row, and a pitch of the first row is different from a pitch of the second row.

Abstract: Provided are a semiconductor device and manufacturing method thereof, and an electronic device. The semiconductor device includes multiple storage cells distributed in a direction perpendicular to a base substrate, the multiple storage cells include multiple transistors and capacitors distributed in different layers and stacked in the direction perpendicular to the base substrate; a word line penetrating different layers and extending in the direction perpendicular to the base substrate; a transistor includes a first source/drain electrode, a second source/drain electrode and a semiconductor layer surrounding a sidewall of the word line; first insulating layers and conductive layers alternately distributed in the direction perpendicular to the base substrate, at least one first hole penetrating the different layers; and the second electrode of the capacitor includes an inner electrode disposed in the first hole on the first electrode.

Abstract: A display device with a narrow bezel is provided. The display device includes a pixel circuit and a driver circuit which are provided on the same plane. The driver circuit includes a selection circuit and a buffer circuit. The selection circuit includes a first transistor. The buffer circuit includes a second transistor. The first transistor has a region overlapping with the second transistor. One of a source and a drain of the first transistor is electrically connected to a gate of the second transistor. One of a source and a drain of the second transistor is electrically connected to the pixel circuit.

Abstract: A semiconductor device structure and method for manufacturing the same are provided. The method includes: providing a substrate; forming a first word line and a second word line extending along a first direction; forming a dielectric material conformally on a first sidewall of the first word line and on a second sidewall of the second word line, wherein the second sidewall of the second word line faces the first sidewall of the first word line; forming a semiconductor material on a sidewall of the dielectric material; and patterning the dielectric material and the semiconductor material to form a gate dielectric structure and a channel layer between the first word line and the second word line.

Abstract: A semiconductor memory device includes a word line extending in a vertical direction, a semiconductor pattern having a ring-shaped horizontal cross-section that extends around the word line, a bit line disposed at a first end of the semiconductor pattern, and a capacitor structure disposed at second end of the semiconductor pattern. The capacitor structure includes a lower electrode layer electrically connected to the second end of the semiconductor pattern, having a ring-shaped horizontal cross-section, and including a connector extending in the vertical direction. A first segment extends in a horizontal direction from an upper end of the connector, and a second segment extends in the horizontal direction from a lower end of the connector. An upper electrode layer surrounded by the lower electrode layer, extends in the vertical direction, and a capacitor dielectric layer is between the lower electrode layer and the upper electrode layer.

Abstract: Methods for forming 3D DRAM leverage L-pad formations to increase memory density. Methods may include etching a substrate to form two Si walls oriented parallel to each other and forming a space therebetween, depositing a plurality of alternating Si layers and SiGe layers using epitaxial growth processes to form horizontal deposition layers on the space between the two Si walls and vertical deposition layers on sidewalls of the two Si walls, depositing a CMP stop layer on the substrate, planarizing the substrate to the CMP stop layer, removing a portion of a top of the two Si walls and forming an L-pad formation, deep etching a pattern of holes into the space between the two Si walls in horizontal portions of the plurality of alternating Si layers and SiGe layers, and forming vertical wordline structures from the pattern of holes in the horizontal portions.

Abstract: A semiconductor memory device includes gate electrodes arranged on a substrate to be spaced apart from each other in a first direction perpendicular to an upper surface of the substrate, an upper insulation layer arranged on an uppermost gate electrode, channel structures penetrating through the upper insulation layer, and the gate electrodes in the first direction, and string selection line cut insulation layers horizontally separating the upper insulation layer and the uppermost gate electrode. Each of the string selection line cut insulation layers includes a protrusion protruding toward the uppermost gate electrode and positioning on the same level as the first gate electrode.

Abstract: A gate insulating film and a gate electrode of non-single crystalline silicon for forming an nMOS transistor are provided on a silicon substrate. Using the gate electrode as a mask, n-type dopants having a relatively large mass number (70 or more) such as As ions or Sb ions are implanted, to form a source/drain region of the nMOS transistor, whereby the gate electrode is amorphized. Subsequently, a silicon oxide film is provided to cover the gate electrode, at a temperature which is less than the one at which recrystallization of the gate electrode occurs. Thereafter, thermal processing is performed at a temperature of about 1000° C., whereby high compressive residual stress is exerted on the gate electrode, and high tensile stress is applied to a channel region under the gate electrode. As a result, carrier mobility of the nMOS transistor is enhanced.

Abstract: A semiconductor structure and a method for manufacturing the semiconductor structure are provided. The semiconductor structure includes a semiconductor base, a bit line and a word line. The semiconductor base includes a substrate and an isolation structure. The isolation structure is arranged above the substrate and configured to isolate a plurality of active regions from each other. The bit line is arranged in the substrate and connected to the plurality of active regions. The word line is arranged in the isolation structure, intersects with the plurality of active regions and surrounds the plurality of active regions. The substrate is a Silicon-On-Insulator (SOI) substrate.