Patents Examined by Kevin Quinto
  • Patent number: 10727118
    Abstract: In a method for manufacturing a semiconductor device, a substrate is provided. Various first metal layers are formed on the substrate. A dielectric structure with through holes is formed over the first metal layers. The through holes expose the first metal layers. A pre-clean operation is performed on the dielectric structure and the first metal layers by using an alcohol base vapor and/or an aldehyde base vapor as a reduction agent. Conductors are formed on the first metal layers. In forming the conductors, the through holes are filled with the conductors.
    Type: Grant
    Filed: April 27, 2018
    Date of Patent: July 28, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jung-Tang Wu, Pao-Sheng Chen, Pei-Hsuan Lee, Szu-Hua Wu, Chih-Chien Chi
  • Patent number: 10727300
    Abstract: A semiconductor device, includes a first conductive type first doping area, a second conductive type second doping area, a source region, a drain region, a gate insulating film, and a gate electrode. The first conductive type first doping area is formed in a substrate region. The second conductive type second doping area is formed in the substrate to be spaced apart from the first conductive type first doping area. The source region is formed in the first conductive type first doping area. The drain region is formed in the second conductive type second doping area. The gate insulating film is formed between the source region and the drain region. A thickness of a first end of the gate insulating film is different than a thickness of a second end of the gate insulating film. The gate electrode formed on the gate insulating film.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: July 28, 2020
    Assignee: MagnaChip Semiconductor, Ltd.
    Inventors: Guk Hwan Kim, Jin Yeong Son
  • Patent number: 10725374
    Abstract: A template substrate includes a pedestal portion on a first surface of a substrate. The template substrate defines an opening region provided in a second surface opposite to the first surface of the substrate. The opening region includes an opening end on a second surface side of the opening region corresponding to the second surface and a bottom surface on a first surface side of the opening region corresponding to the first surface. An area of the opening end is different from an area of the bottom surface.
    Type: Grant
    Filed: March 2, 2018
    Date of Patent: July 28, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Anupam Mitra
  • Patent number: 10720593
    Abstract: A display device including a light emitting element including a first electrode, a light emitting layer and a plurality of organic layers including a hole transport layer above the first electrode, and a second electrode above the plurality of organic layers, and an insulation layer having an opening part exposing a part of the first electrode and covering a periphery side part of the first electrode, wherein when a hole mobility of the light emitting layer is ?h1 and a hole mobility of the hole transport layer is ?h2 then ? h ? ? 2 ? h ? ? 1 ? 10 3 and when a periphery length of the part of the first electrode exposed by the opening part is L and an area of the first electrode exposed by the opening part is S0 then L S 0 ? 0.
    Type: Grant
    Filed: February 28, 2019
    Date of Patent: July 21, 2020
    Assignee: Japan Display Inc.
    Inventor: Tsuyoshi Uemura
  • Patent number: 10720403
    Abstract: A package includes a first die and a second die. The first die includes a first substrate and a first metal pad overlying the first substrate. The second die includes a second substrate and a second metal pad overlying the second substrate. A molding compound molds the first die and the second die therein. The molding compound has a first portion between the first die and the second die, and a second portion, which may form a ring encircles the first portion. The first portion and the second portion are on opposite sides of the first die. The first portion has a first top surface. The second portion has a second top surface higher than the first top surface.
    Type: Grant
    Filed: August 13, 2018
    Date of Patent: July 21, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Hao Tsai, Li-Hui Cheng, Jui-Pin Hung, Jing-Cheng Lin
  • Patent number: 10720357
    Abstract: A method of forming a semiconductor device. The method may include providing a device structure, where the device structure comprises a masked portion and a cut portion. The masked portion may comprise a mask covering at least one semiconductor fin of a fin array, and the cut portion may comprise a trench, where the trench exposes a semiconductor fin region of the fin array. The method may further include providing an exposure of the trench to oxidizing ions, the oxidizing ions to transform a semiconductor material into an oxide.
    Type: Grant
    Filed: March 1, 2018
    Date of Patent: July 21, 2020
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Min Gyu Sung, Naushad K Variam, Sony Varghese, Johannes Van Meer, Jae Young Lee, Jun Lee
  • Patent number: 10714423
    Abstract: A method comprises forming a trench extending through an interlayer dielectric layer over a substrate and partially through the substrate, depositing a photoresist layer over the trench, wherein the photoresist layer partially fills the trench, patterning the photoresist layer to remove the photoresist layer in the trench and form a metal line trench over the interlayer dielectric layer, filling the trench and the metal line trench with a conductive material to form a via and a metal line, wherein an upper portion of the trench is free of the conductive material and depositing a dielectric material over the substrate, wherein the dielectric material is in the upper portion of the trench.
    Type: Grant
    Filed: November 2, 2017
    Date of Patent: July 14, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yung-Chi Lin, Hsin-Yu Chen, Lin-Chih Huang, Tsang-Jiuh Wu, Wen-Chih Chiou
  • Patent number: 10700164
    Abstract: Semiconductor devices may include a diffusion prevention insulation pattern, a plurality of conductive patterns, a barrier layer, and an insulating interlayer. The diffusion prevention insulation pattern may be formed on a substrate, and may include a plurality of protrusions protruding upwardly therefrom. Each of the conductive patterns may be formed on each of the protrusions of the diffusion prevention insulation pattern, and may have a sidewall inclined by an angle in a range of about 80 degrees to about 135 degrees to a top surface of the substrate. The barrier layer may cover a top surface and the sidewall of each if the conductive patterns. The insulating interlayer may be formed on the diffusion prevention insulation pattern and the barrier layer, and may have an air gap between neighboring ones of the conductive patterns.
    Type: Grant
    Filed: February 13, 2019
    Date of Patent: June 30, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin-Nam Kim, Rak-Hwan Kim, Byung-Hee Kim, Jong-Min Baek, Sang-Hoon Ahn, Nae-In Lee, Jong-Jin Lee, Ho-Yun Jeon, Eun-Ji Jung
  • Patent number: 10690975
    Abstract: Provided are an active-matrix substrate, a method for manufacturing the same, and a display device, which render it possible to inhibit electrostatic discharge from occurring during the process of manufacturing a display panel and suppress manufacturing cost. An IGZO film, which is positioned between a silicon oxide film included in a gate insulating film and an etch-stop layer, is annealed at 200 to 350° C. after a passivation film for protecting a TFT is formed. As a result, the passivation film is annealed, and the IGZO film is changed from a conductor to a semiconductor. Consequently, it is not only possible to suppress the occurrence of ESD, but also possible to eliminate the need to sever an electrostatic discharge prevention circuit from a display panel, resulting in a reduced cost of manufacturing a display device.
    Type: Grant
    Filed: March 24, 2017
    Date of Patent: June 23, 2020
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Tohru Okabe, Hirohiko Nishiki, Shinji Nakajima, Izumi Ishida, Shogo Murashige
  • Patent number: 10686100
    Abstract: A light-emitting diode (LED) device (e.g., AlGaInP LED) includes a transparent substrate, an epitaxial structure defining an isolation trench and an epitaxial structure, an insulating passivation layer, a P electrode and an N electrode. The epitaxial structure is disposed above the transparent substrate. The isolation trench divides the epitaxial structure into a first portion and a second portion. The at least one through hole extends through the first portion. At least a portion of the insulating passivation layer is disposed in the isolation trench. The P electrode is disposed above the first portion of the epitaxial structure and in the at least one through hole. The N electrode is disposed above the second portion of the epitaxial structure. A top surface of the P electrode is horizontally aligned with a top surface of the N electrode.
    Type: Grant
    Filed: August 23, 2018
    Date of Patent: June 16, 2020
    Assignee: Yangzhou Changelight Co., Ltd.
    Inventors: Zhou Xu, Bo Li, Kaixuan Chen, Yuren Peng, Guoqing Zhang
  • Patent number: 10686058
    Abstract: A method of manufacturing a trench MOSFET can include: forming an epitaxial semiconductor layer having a first doping type on a semiconductor substrate; forming a trench extending from a first surface of the epitaxial semiconductor layer to an internal portion of the epitaxial semiconductor layer; forming a first insulating layer and a shield conductor occupying a lower portion of said trench, where the first insulating layer is located on a lower sidewall surface and a bottom surface of the trench and separates the shield conductor from the epitaxial semiconductor layer; forming a second insulating layer covering a top surface of said shield conductor, where the second insulating layer is patterned by using a hard mask; forming a gate dielectric layer and a gate conductor occupying an upper portion of the trench; and forming a body region, a source region, and a drain electrode.
    Type: Grant
    Filed: October 2, 2018
    Date of Patent: June 16, 2020
    Assignee: Silergy Semiconductor Technology (Hangzhou) LTD
    Inventors: Jinyong Cai, Zhongping Liao
  • Patent number: 10686067
    Abstract: A semiconductor device (A1) includes a semiconductor layer having a first face with a trench (3) formed thereon and a second face opposite to the first face, a gate electrode (41), and a gate insulating layer (5). The semiconductor layer includes a first n-type semiconductor layer (11), a second n-type semiconductor layer (12), a p-type semiconductor layer (13), and an n-type semiconductor region (14). The trench (3) is formed so as to penetrate through the p-type semiconductor layer (13) and to reach the second n-type semiconductor layer (12). The p-type semiconductor layer (13) includes an extended portion extending to a position closer to the second face of the semiconductor layer than the trench (3) is. Such structure allows suppressing dielectric breakdown in the gate insulating layer (5).
    Type: Grant
    Filed: April 9, 2019
    Date of Patent: June 16, 2020
    Assignee: ROHM CO., LTD.
    Inventor: Yuki Nakano
  • Patent number: 10672904
    Abstract: A semiconductor device and the method of manufacturing the same are provided. The semiconductor device comprises a substrate, a source region, a drain region, a filed plate and a gate electrode. The source region is of a first conductivity type located at a first side within the substrate. The drain region is of the first conductive type located at a second side within the substrate opposite to the first side. The field plate is located over the substrate and between the source region and the drain region. A portion of the gate electrode is located over the field plate.
    Type: Grant
    Filed: April 19, 2019
    Date of Patent: June 2, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yogendra Yadav, Chi-Chih Chen, Ruey-Hsin Liu, Chih-Wen Yao
  • Patent number: 10672648
    Abstract: A method of forming a semiconductor memory device includes following steps. First of all, a dielectric layer is formed on a semiconductor substrate, and a conductive pad is formed in the dielectric layer. Then, a stacked structure is formed on the dielectric layer, and the stacked structure includes a first layer, a second layer and a third layer stacked one over another on the conductive pad. Next, a patterned mask layer is formed on the stacked structure, and a portion of the stacked structure is removed, to form an opening in the stacked structure, with the opening having a tapered sidewall in the second layer and the first layer. After that, the tapered sidewall of the opening in the second layer is vertically etched, to form a contact opening in the stacked structure. Finally, the patterned mask layer is removed.
    Type: Grant
    Filed: March 27, 2018
    Date of Patent: June 2, 2020
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Feng-Yi Chang, Fu-Che Lee, Yi-Wang Zhan
  • Patent number: 10673206
    Abstract: A semiconductor device includes an upper and lower mirror. At least one active region for light generation is between the upper and lower mirror. At least one cavity spacer layer is between at least one of the upper and lower mirror and the active region. The device includes an inner mode confinement region and an outer current blocking region. A depleted heterojunction current blocking region (DHCBR) including a depleting impurity is within the outer current blocking region of ?1 of the upper mirror, lower mirror, and the first active region. A middle layer including a conducting channel is within the inner mode confinement region that is framed by the DHCBR. The DHCBR forces current flow into the conducting channel during normal operation of the light source.
    Type: Grant
    Filed: August 26, 2019
    Date of Patent: June 2, 2020
    Assignee: sdPhotonics LLC
    Inventor: Dennis G. Deppe
  • Patent number: 10658199
    Abstract: A method of manufacturing a semiconductor device includes placing a polymer raw material mixture over a substrate. The polymer raw material may include a polymer precursor, a photosensitizer, and an additive. The polymer raw material mixture is exposed to radiation to form a dielectric layer and cured at a temperature of between about 150° C. and about 230° C.
    Type: Grant
    Filed: December 2, 2016
    Date of Patent: May 19, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sih-Hao Liao, Yu-Hsiang Hu, Hung-Jui Kuo, Chen-Hua Yu
  • Patent number: 10658292
    Abstract: A semiconductor device or structure includes a first pattern metal layer disposed between a first supply metal tract and a second supply metal tract, the first pattern metal layer comprising an internal route and a power route. A follow pin couples the first supply metal to the power route. The second supply metal tract is wider than the first supply metal tract. The first supply metal tract has a thickness substantially same as the first pattern metal layer. The first supply metal tract comprises a first metal and a follow pin comprises a second metal.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: May 19, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Shih-Wei Peng, Chih-Liang Chen, Charles Chew-Yuen Young, Hui-Ting Yang, Jiann-Tyng Tzeng, Wei-Cheng Lin
  • Patent number: 10658518
    Abstract: Magnesium Zinc Oxide (MZO)—based high voltage thin film transistor (MZO-HVTFT) is built on a transparent substrate, such as glass. The device has the circular drain and ring-shaped source and gate to reduce non-uniformity of the electric field distribution. Controlled Mg doping in the channel and modulated Mg doping in a transition layer located at the channel-gate dielectric interface improve the device's operating stability and increase its blocking voltage capability over 600V. The MZO HVTFT can be used for fabricating the micro-inverter in photovoltaic system on glass (PV-SOG), and for self-powered smart glass.
    Type: Grant
    Filed: August 18, 2017
    Date of Patent: May 19, 2020
    Assignee: RUTGERS, THE STATE UNIVERSITY OF NEW JERSEY
    Inventors: Yicheng Lu, Wen-Chiang Hong, Chieh-Jen Ku, Kuang Sheng, Rui Li
  • Patent number: 10644064
    Abstract: An embodiment integrates memory, such as spin-torque transfer magnetoresistive random access memory (STT-M RAM) within a logic chip. The STT-MRAM includes a magnetic tunnel junction (MTJ) that has an upper MTJ layer, a lower MTJ layer, and a tunnel barrier directly contacting the upper MTJ layer and the lower MTJ layer; wherein the upper MTJ layer includes an upper MTJ layer sidewall and the lower MTJ layer includes a lower MTJ sidewall horizontally offset from the upper MTJ layer. Another embodiment includes a memory area, comprising a MTJ, and a logic area located on a substrate; wherein a horizontal plane intersects the MTJ, a first Inter-Layer Dielectric (ILD) material adjacent the MTJ, and a second ILD material included in the logic area, the first and second ILD materials being unequal to one another. Other embodiments are described herein.
    Type: Grant
    Filed: April 20, 2018
    Date of Patent: May 5, 2020
    Assignee: Intel Corporation
    Inventors: Kevin J. Lee, Tahir Ghani, Joseph M. Steigerwald, John H. Epple, Yih Wang
  • Patent number: 10622508
    Abstract: A method for manufacturing an optoelectronic component includes providing a growth substrate; applying a succession of semiconductor layers; structuring the succession of semiconductor layers; applying a sacrificial layer; depositing a metal layer; optionally planarizing using a dielectric material; forming a second terminal contact through the active region; applying a permanent support; and detaching the growth substrate and exposing the metal layer.
    Type: Grant
    Filed: February 24, 2017
    Date of Patent: April 14, 2020
    Assignee: OSRAM OLED GmbH
    Inventors: Dominik Scholz, Alexander F. Pfeuffer, Isabel Otto