Abstract: A method for forming a semiconductor memory structure includes forming an isolation structure surrounding an active region in a substrate. The method also includes forming a first trench to separate the active region into a first active region and a second active region. The method also includes forming a bit line over the bottom portion of the first trench. The method also includes forming a word line surrounding the first active region and the second active region and over the bit line. The method also includes self-aligned forming a contact over the first active region and the second active region. The method also includes forming a capacitor over the contact.

Abstract: A cell array includes a substrate and a conductive line. The substrate has active areas in the substrate. The conductive line is disposed across the active areas and includes work function nodes and line sections which are horizontally and alternately arranged with work function nodes, in which each work function node is between two of the active areas.

Abstract: The present application provides a semiconductor structure and a manufacturing method thereof, relates to the technical field of semiconductors. The manufacturing method of a semiconductor structure includes: providing a substrate; forming a plurality of laminated structures arranged at intervals on the substrate, the laminated structure includes a first conductive layer, an insulating layer, and a second conductive layer, and at least one of the first conductive layer and the second conductive layer is a semi-metal layer; forming a channel layer covering the laminated structures, and a dielectric layer covering the channel layer; and forming word lines (WLs) extending along a first direction, the WL includes a plurality of contact parts and a connecting part connecting adjacent contact parts, the contact part surrounds and is in contact with a side surface of the dielectric layer, and the contact part is opposite to at least a part of the insulating layer.

Abstract: A memory structure and its manufacturing method are provided. The memory structure includes a substrate, a tunnel dielectric layer on the substrate and a floating gate on the tunnel dielectric layer. The substrate has a source region and a drain region, and the source region and the drain region are formed on two opposite sides of the floating gate. The memory structure also includes an inter-gate dielectric layer on the floating gate and a control gate on the inter-gate dielectric layer. The memory structure further includes a doping region buried in the floating gate, wherein a sidewall of the doping region is exposed at a sidewall of the floating gate. Also, the doping region and the inter-gate dielectric layer are separated from each other.

Abstract: Systems, methods and apparatus are provided for an array of vertically stacked memory cells having vertically oriented access devices having a first source/drain region and a second source drain region vertically separated by a channel region, and gates opposing the channel region, vertically oriented access lines coupled to the gates and separated from a channel region by a gate dielectric. The memory cells have horizontally oriented storage nodes coupled to the first source/drain region and horizontally oriented digit lines coupled to the second source/drain regions.

Abstract: Systems, methods and apparatus are provided for forming layers of a first dielectric material, a semiconductor material, and a second dielectric material in repeating iterations vertically to form a vertical stack and forming a vertical opening using an etchant process to expose vertical sidewalls in the vertical stack. A seed material that is selective to the semiconductor material is deposited over the vertical stack and the vertical sidewalls in the vertical stack and the seed material is processed such that the seed material advances within the semiconductor material such that it transforms a crystalline structure of a portion of the semiconductor material.

Abstract: The disclosure relates to a highly integrated memory device and a method for manufacturing the same. According to the disclosure, a memory device comprises a lower structure, an active layer horizontally oriented parallel to a surface of the lower structure, a bit line connected to a first end of the active layer and vertically oriented from the surface of the lower structure, a capacitor connected to a second end of the active layer, a word line horizontally oriented to be parallel with the active layer along a side surface of the active layer, and a fin channel layer horizontally extending from one side surface of the active layer, wherein the word line includes a protrusion covering the fin channel layer.

Abstract: The present disclosure provides a semiconductor structure having a memory structure and a method for manufacturing the semiconductor structure. The semiconductor structure includes a first layer, a second layer over the first layer, a third layer over the second layer, and a trench capacitor. The trench capacitor is disposed in a trench penetrating the first layer, the second layer, and the third layer. The trench capacitor includes a bottom metal layer, a middle insulating layer, and a top metal layer. The bottom metal layer covers a side wall of the first layer, a side wall of the second layer, and a first portion of a side wall of the third layer. The middle insulating layer covers the bottom metal layer and a second portion of the side wall of the third layer. The top metal layer covers the middle insulating layer.

Abstract: A transistor structure can include a semiconductor-on-insulator substrate that includes an upper substrate region separated from a lower substrate region by a buried insulator. Shallow halo implant regions can be formed in an upper substrate region having a peak concentration at a first depth within the upper substrate region. Deep halo implant regions can be formed in the upper substrate region having a peak concentration at a second depth lower than the first depth. An epitaxial layer can be formed on top of the upper substrate region and below the control gate. Source and drain regions both of a second conductivity type formed in at least the epitaxial layer. In some embodiments, a lower substrate region can be biased for a double-gate effect.

Abstract: A front surface of a semiconductor wafer is rapidly heated by irradiation of a flash of light. Temperature of the front surface of the semiconductor wafer is measured at predetermined intervals after the irradiation of the flash of light, and is sequentially accumulated to acquire a temperature profile. From the temperature profile, an average value and a standard deviation are each calculated as a characteristic value. It is determined that the semiconductor wafer is cracked when an average value of the temperature profile deviates from the range of ±5? from a total average of temperature profiles of a plurality of semiconductor wafers or when a standard deviation of the temperature profile deviates from the range of 5? from the total average thereof of the plurality of semiconductor wafers.

Abstract: A butted contact structure is provided. In one embodiment, a structure includes a first transistor on a substrate, the first transistor comprising a first source or drain region, a first gate, and a first gate spacer being disposed between the first gate and the first source or drain region. The structure includes a second transistor on the substrate, the second transistor comprising a second source or drain region, a second gate, and a second gate spacer being disposed between the second gate and the second source or drain region. The structure includes a butted contact disposed above and extending from the first source or drain region to at least one of the first or second gate, a portion of the first gate spacer extending a distance into the butted contact to separate a first bottom surface of the butted contact from a second bottom surface of the butted contact.

Abstract: A method used in forming an array of vertical transistors comprises forming pillars individually comprising an upper source/drain region, a channel region vertically below the upper source/drain region, and sacrificial material above the upper source/drain region. Intervening material is about the sacrificial material of individual of the pillars. The intervening material and the sacrificial material comprise different compositions relative one another. Horizontally-elongated and spaced conductive gate lines are formed individually operatively aside the channel region of the individual pillars. The sacrificial material is removed to expose the upper source/drain region of the individual pillars and thereby form an opening in the intervening material directly above the upper source/drain region of the individual pillars.

Abstract: Systems, methods and apparatus are provided for support pillars in vertical three-dimensional (3D) memory. An example method includes a method for forming arrays of vertically stacked memory cells, having horizontally oriented access devices and horizontally oriented storage nodes. The method includes depositing alternating layers of a dielectric material and a sacrificial material in repeating iterations to form a vertical stack. A plurality of spaced, first vertical openings are formed through the vertical stack adjacent areas where storage nodes will be formed. Support-pillar material is deposited in the plurality of spaced, first vertical openings to form structural support pillars. Second vertical openings are formed through the vertical stack adjacent the structural support pillars to define elongated vertical columns with first sidewalls of the alternating layers.

Abstract: Systems, methods and apparatus are provided for an array of vertically stacked memory cells. The vertically stacked memory cells have horizontally oriented access devices having a first source/drain region, a channel region, and a second source drain and storage nodes that are vertically separated from the access devices.

Abstract: The invention provides a semiconductor memory cell, the semiconductor memory cell includes a substrate having a first conductivity type, a doped region in the substrate, wherein the doped region has a second conductivity type, and the first conductivity type is complementary to the second conductivity type, a capacitor insulating layer and an upper electrode on the doped region, a transistor on the substrate, and a shallow trench isolation disposed between the transistor and the capacitor insulating layer, and the shallow trench isolation is disposed in the doped region.

Abstract: A method of manufacturing a light emitting panel, a light emitting panel, and a display device are disclosed. The method includes providing a substrate, forming a first metal layer on the substrate, performing an oxidation process to the first metal layer to form an oxide layer on the first metal layer, forming a photoresist layer on the oxide layer, patterning the photoresist layer, the oxide layer, and the substrate, and stripping a patterned photoresist layer, and sequentially forming a first passivation layer, a color resist layer, a second passivation layer, and an indium tin oxide film layer on the oxide layer.

Abstract: Disclosed are semiconductor memory devices and methods of fabricating the same. The method including forming a mold structure by alternately stacking a plurality of first insulating layers and a plurality of second insulating layers on a substrate, patterning the mold structure to form a first trench that exposes a first inner sidewall of the mold structure, growing a vertical semiconductor layer in the first trench such that a vertical semiconductor layer covers the first inner sidewall, using the substrate as a seed to, patterning the mold structure to form a second trench that exposes a second inner sidewall of the mold structure, forming a plurality of recesses by selectively removing the second insulating layers from the mold structure through the second trench, and horizontally growing a plurality of horizontal semiconductor layers in corresponding recesses, using the vertical semiconductor layer as a seed may be provided.

Abstract: A DRAM device and its manufacturing method are provided. The DRAM device includes an interlayer dielectric layer and capacitor units framed on a substrate. The interlayer dielectric layer has capacitor unit accommodating through holes and includes a first support layer, a composite dielectric layer, and a second support layer sequentially formed on the substrate. The composite dielectric layer includes at least one first insulating layer and second insulating layer alternately stacked. Each capacitor unit accommodating through hole forms a first opening in the second insulating layer and forms a second opening communicating with the first opening in the first insulating layer. The second opening is wider than the first opening. The capacitor units are formed in the capacitor unit accommodating through holes. The top of the capacitor unit is higher than the top surface of the interlayer dielectric layer and defines a recessed region.

Abstract: A semiconductor memory device includes a memory cell array of a three-dimensional structure including a plurality of memory cells repeatedly arranged in a first horizontal direction and a second horizontal direction that are parallel with a main surface of a substrate and cross each other on the substrate and in a vertical direction perpendicular to the main surface, wherein each of the plurality of memory cells includes three transistors. A method of manufacturing a semiconductor memory device includes forming simultaneously a plurality of memory cells arranged in a row in a vertical direction on a substrate, wherein each of the plurality of memory cells includes three transistors.

Abstract: An electronic device having a first component carrier and an electronic component which is surface mounted on or embedded within the first component carrier. The electronic device further has a second component carrier. The first component carrier together with the electronic component is at least partially embedded within the second component carrier.