Abstract: A method of forming a microelectronic device comprises forming a microelectronic device structure assembly comprising memory cells, digit lines coupled to the memory cells, contact structures coupled to the digit lines, word lines coupled to the memory cells, additional contact structures coupled to the word lines, and isolation material surrounding the contact structures and the additional contact structures and overlying the memory cells. An additional microelectronic device structure assembly is formed and comprises control logic devices, further contact structures coupled to the control logic devices, and additional isolation material surrounding the further contact structures and overlying the control logic devices.

Abstract: A semiconductor memory device includes: a peripheral circuit portion including an interconnection; first and second word line stacks that are spaced apart from each other over the peripheral circuit portion, the first and second word line stacks including word lines, respectively; an alternating stack of dielectric layers that are positioned over the peripheral circuit portion and disposed between the first and second word line stacks; a first contact plug penetrating the alternating stack to be coupled to the interconnection; a second contact plug coupled to the word lines of the first and second word line stacks; a first line-shape supporter between the first word line stack and the alternating stack, and extending vertically from the peripheral circuit portion; and a second line-shape supporter between the second word line stack and the alternating stack, and extending vertically from the peripheral circuit portion.

Abstract: The present disclosure provides to a semiconductor memory device. The semiconductor memory device includes a substrate having a cell area and a peripheral area; and a first bit line structure disposed on and protruding from a surface of the cell area. The first bit line structure is sandwiched by a pair of air gaps and a barrier layer is conformally overlaying the air gaps adjacent to the sidewalls of the first bit line structure and the cell area. The first bit line structure has a sidewall and an ascending top portion, and a landing pad is disposed over the ascending top portion and the sidewalls of the first bit line structure. The landing pad has an inclined surface corresponding to the ascending top portion of the first bit line structure.

Abstract: Examples herein relate to three-dimensional (3D) dynamic random access memory (DRAM) and corresponding methods. In an example, a film stack is formed on a substrate. The film stack includes multiple unit stacks, each having, sequentially, a first dielectric layer, a semiconductor layer, and a second dielectric layer. A first opening is formed through the film stack. The second dielectric layer is pulled back from the first opening forming a first lateral recess. A gate structure is formed in the first lateral recess and disposed on a portion of the semiconductor layer. A second opening, laterally disposed from where the first opening was formed, is formed through the film stack. The portion of the semiconductor layer is pulled back from the second opening forming a second lateral recess. A capacitor is formed in a region where the second lateral recess was disposed and contacting the portion of the semiconductor layer.

Abstract: Provided herein may be a semiconductor device. The semiconductor device may include a first stacked body including a first stacked insulating layer and a first stacked conductive layer that are alternately stacked; a capacitor plug passing through the first stacked body; and a capacitor multi-layered layer configured to enclose the capacitor plug. The capacitor plug may include metal.

Abstract: A method for manufacturing a semiconductor device is provided.

Abstract: A method for forming a semiconductor device, includes: forming a metal layer on a semiconductor substrate; forming a dielectric layer over the metal layer; etching a top portion of the dielectric layer; after etching the top portion of the dielectric layer, removing first mist from a bottom portion of the dielectric layer; removing the bottom portion of the dielectric layer to expose the metal layer; performing a pre-clean operation, using an alcohol base vapor or an aldehyde base vapor, on the dielectric layer and the metal layer; and forming a conductor extending through the dielectric layer and in contact with the metal layer.

Abstract: A multiple gate dielectrics and dual work-functions field effect transistor (MGO-DWF-FET) is provided on an active region of a semiconductor substrate. The MGO-DWF-FET includes a first functional gate structure including a U-shaped first high-k gate dielectric material layer and a first work-function metal-containing structure, and a laterally adjacent, and contacting, second functional gate structure that includes a U-shaped second high-k gate dielectric material layer and a second work-function metal-containing structure. The first functional gate structure has a gate length that differs from a gate length of the second functional gate structure.

Abstract: The present disclosure relates to a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a substrate including a peripheral region, wherein the peripheral region includes a wire lead-out area, and the substrate is arranged with a plurality of discrete bit line structures; a dielectric layer formed between the adjacent bit line structures, wherein the peripheral region is arranged with a first contact hole; a wire lead-out area with a second through hole; a filling layer filling part of a first contact hole, wherein a remaining part of the first contact hole is defined as a first through hole; a first conductive layer located in the first through hole and the second through hole; and a conductive connecting wire located over the dielectric layer and being in contact with the first conductive layer in the wire lead-out area.

Abstract: A method includes forming a plurality of first line-shaped mask patterns over a substrate including a memory cell region and an array edge region; forming a plurality of second line-shaped mask patterns over the plurality of first line-shaped mask patterns; removing first portions from the plurality of first line-shaped mask patterns in the memory cell region to leave a plurality of island-shaped mask patterns above the memory cell region; removing second portions from the plurality of first line-shaped mask patterns in the array edge region to leave a holes-provided mask pattern above the array edge region; forming a mask pattern which includes a plurality of holes provided on portions; and forming, with the mask pattern which includes the plurality of holes, a plurality of contact holes in the array edge region to provide a plurality of contact electrodes connected to a plurality of word-lines.

Abstract: Nanowire structures having wrap-around contacts are described. For example, a nanowire semiconductor device includes a nanowire disposed above a substrate. A channel region is disposed in the nanowire. The channel region has a length and a perimeter orthogonal to the length. A gate electrode stack surrounds the entire perimeter of the channel region. A pair of source and drain regions is disposed in the nanowire, on either side of the channel region. Each of the source and drain regions has a perimeter orthogonal to the length of the channel region. A first contact completely surrounds the perimeter of the source region. A second contact completely surrounds the perimeter of the drain region.

Abstract: A method comprises forming a trench extending through an interlayer dielectric layer over a substrate and partially through the substrate, depositing a photoresist layer over the trench, wherein the photoresist layer partially fills the trench, patterning the photoresist layer to remove the photoresist layer in the trench and form a metal line trench over the interlayer dielectric layer, filling the trench and the metal line trench with a conductive material to form a via and a metal line, wherein an upper portion of the trench is free of the conductive material and depositing a dielectric material over the substrate, wherein the dielectric material is in the upper portion of the trench.

Abstract: Techniques are disclosed for forming transistors including source and drain (S/D) regions employing double-charge dopants. As can be understood based on this disclosure, the use of double-charge dopants for group IV semiconductor material (e.g., Si, Ge, SiGe) either alone or in combination with single-charge dopants (e.g., P, As, B) can decrease the energy barrier at the semiconductor/metal interface between the source and drain regions (semiconductor) and their respective contacts (metal), thereby improving (by reducing) contact resistance at the S/D locations. In some cases, the double-charge dopants may be provided in a top or cap S/D portion of a given S/D region, for example, so that the double-charge doped S/D material is located at the interface of that S/D region and the corresponding contact. The double-charge dopants can include sulfur (S), selenium (Se), and/or tellurium (Te). Other suitable group IV material double-charge dopants will be apparent in light of this disclosure.

Abstract: A semiconductor memory device includes: a bit line extending on a substrate in a vertical direction; a transistor body part including a first source-drain region, a monocrystalline channel layer, and a second source-drain region that are sequentially arranged in a first horizontal direction and connected to the bit line; gate electrode layers extending in a second horizontal direction that is orthogonal to the first horizontal direction, with a gate dielectric layer between the gate electrode layers and the monocrystalline channel layer, and covering upper and lower surfaces of the monocrystalline channel layer; and a cell capacitor including a lower electrode layer, a capacitor dielectric layer, and an upper electrode layer at a side of the transistor body that is opposite to the bit line in the first horizontal direction and is connected to the second source-drain region.

Abstract: Some embodiments include an integrated transistor having an active region comprising semiconductor material. A conductive gating structure is adjacent to the active region. The conductive gating structure includes an inner region proximate the active region and includes an outer region distal from the active region. The inner region includes a first material containing titanium and nitrogen, and the outer region includes a metal-containing second material. The second material has a higher conductivity than the first material. Some embodiments include integrated assemblies. Some embodiments include methods of forming integrated assemblies.

Abstract: A method of manufacturing a semiconductor device includes placing a polymer raw material mixture over a substrate. The polymer raw material may include a polymer precursor, a photosensitizer, and an additive. The polymer raw material mixture is exposed to radiation to form a dielectric layer and cured at a temperature of between about 150° C. and about 230° C.

Abstract: In a semiconductor device, a first stack is positioned over substrate and includes a first pair of transistors and a second pair of transistors stacked over the substrate. A second stack is positioned over the substrate and adjacent to the first stack. The second stack includes a third pair of transistors and a fourth pair of transistors stacked over the substrate. A first capacitor is stacked with the first and second stacks. A second capacitor is positioned adjacent to the first capacitor and stacked with the first and second stacks. A first group of the transistors in the first and second stacks is coupled to each other to form a static random-access memory cell. A second group of the transistors in the first and second stacks is coupled to the first and second capacitors to form a first dynamic random-access memory (DRAM) cell and a second DRAM cell.

Abstract: A semiconductor structure includes a semiconductor substrate including a first active region and a chop region. The semiconductor structure also includes a source/drain region disposed in the first active region, an isolation structure disposed in the chop region, and a gate structure extending at least across the isolation structure in the chop region. The gate structure includes a gate electrode layer and a gate lining layer lining on the gate electrode layer. The gate lining layer includes a first portion having an upper surface that is lower than a bottom surface of the source/drain region.

Abstract: A semiconductor memory device, including a first semiconductor pattern, and a second semiconductor pattern separated from the first semiconductor pattern in a vertical direction; a first bit line electrically connected to a first source/drain region of the first semiconductor pattern, and a second bit line electrically connected to a first source/drain region of the second semiconductor pattern; a word line structure in contact with the first semiconductor pattern and the second semiconductor pattern; and a first data storage element electrically connected to a second source/drain region of the first semiconductor pattern, and a second data storage element electrically connected to a second source/drain region of the second semiconductor pattern, wherein the first semiconductor pattern and the second semiconductor pattern are monocrystalline, and wherein a crystal orientation of the first semiconductor pattern is different from a crystal orientation of the second semiconductor pattern.

Abstract: Memory devices and methods of manufacturing memory devices are provided. Described are devices and methods where 3D pitch multiplication decouples high aspect ratio etch width from cell width, creating small cell active area pitch to allow for small DRAM die size.