Abstract: Systems, methods and apparatus are provided for a semiconductor structure. An example method includes a method for forming a contact surface on a vertically oriented access devices. The method includes forming a first source/drain region and a second source/drain region vertically separated by a channel region, forming a sacrificial etch stop layer on a first side of the second source/drain region, wherein the channel region is in contact with a second side of the second source/drain region, forming a dielectric layer on a first side of the sacrificial etch stop layer, where the second source/drain region is connected to a second side of the sacrificial etch stop layer, removing the dielectric layer using a first etch process to expose the sacrificial etch stop layer, and removing the sacrificial etch stop layer using a second etch process to form a contact surface on the second source/drain region.

Abstract: Systems, methods and apparatus are provided for an array of vertically stacked memory cells having horizontally oriented access devices and access lines, and vertically oriented digit lines having a first source/drain region and a second source drain region separated by a channel region, and gates opposing the channel region, horizontal oriented access lines coupled to the gates and separated from a channel region by a gate dielectric. The memory cells have horizontally oriented storage nodes coupled to the second source/drain region of the horizontally oriented access devices. The vertically oriented digit lines are formed in direct electrical contact with the first source/drain regions of the horizontally oriented access devices. A vertically oriented body contact line is integrated to form the body contact to the body region of the horizontally oriented access device and separate from the first source/drain region and the vertically oriented digit lines by a dielectric.

Abstract: A semiconductor device includes: a first bit line extending in a first direction; a first word line extending in a second direction intersecting the first direction; a first transistor located at a first intersection of the first word line and the first bit line, the first transistor being connected to the first word line and the first bit line; a first capacitor electrically connected to the first transistor, the first capacitor being located at a first part of the first intersection; a second capacitor electrically isolated from the first transistor, the second capacitor being located at a second part of the first intersection; and a second transistor electrically connected to the second capacitor, the first capacitor and the second capacitor being located between the first transistor and the second transistor.

Abstract: A memory structure may be provided, including a substrate, and a first well region, a second well region, and a third well region arranged within the substrate, where the first well region and the third well region may have a first conductivity type, and the second well region may have a second conductivity type different from the first conductivity type, and where the second well region may be arranged laterally between the first well region and the third well region. The memory structure may further include a first gate structure and a second gate structure arranged over the second well region. The first gate structure may extend over the third well region and the second gate structure may extend over the first well region.

Abstract: A flat no-leads package, the flat no-leads package includes a leadframe for electrically connecting an integrated circuit (IC) chip which in a mounted configuration is arranged in a center portion of the flat no-leads package. The leadframe has at least one RF lead pin; and an isolating encapsulation which is at least partially encapsulating the leadframe such that contact surfaces of the leadframe are electrically contactable at least from a bottom side of the flat no-leads package; wherein at least one of the RF lead pin has a first and second contact surfaces. A cross-section of the RF lead pin increases from the first contact surface to the second contact surface both in a horizontal direction and in a direction vertical thereto. Further, a printed circuit board having a flat no-leads package and a measurement device having a flat no-leads package are provided.

Abstract: A DRAM including a silicon substrate, buried word lines, and active areas is provided. The silicon substrate has a carrier surface. The buried word lines are buried in the silicon substrate. The active areas are located on the carrier surface. The buried word lines intersect the active area. Each of the buried word lines has a first width in one of the active area, and has a second width outside the active areas, and the first width is larger than the second width. A manufacturing method of DRAM is also provided.

Abstract: A method for manufacturing a DRAM includes: forming a hard mask layer on a substrate with an opening therein; forming a dielectric layer on a sidewall of the opening; forming a first barrier layer and a first conductor layer in the opening; performing a first dry etching and a first wet etching processes to respectively partially remove the first barrier layer and the first conductor layer, to expose the dielectric layer on upper sidewall; forming a second barrier layer in the opening; forming a mask layer in the opening to cover the second barrier layer; removing a part of the second barrier layer and the mask layer to expose the dielectric layer on the upper sidewall of the opening; and forming a second conductor layer in the opening.

Abstract: Disclosed is a three-dimensional semiconductor device comprising channel regions that penetrate the stack structure and extend in a direction perpendicular to a top surface of the first substrate, a first interlayer dielectric layer on the stack structure, and a peripheral circuit structure on the first interlayer dielectric layer. The peripheral circuit structure includes peripheral circuit elements on a first surface of a second substrate. The peripheral circuit elements are electrically connected to the channel regions and at least one of the gate electrodes. The first substrate has a first crystal plane parallel to the top surface thereof. The second substrate has a second crystal plane parallel to the first surface thereof. An arrangement direction of atoms of the first crystal plane intersects an arrangement direction of atoms of the second crystal plane.

Abstract: A semiconductor device is disclosed including a wire bonded die stack where the bond wires skip dies in the die stack to provide bond wires having a long length. In one example, the semiconductor dies are stacked on top of each other with offsets along two orthogonal axes so that the dies include odd numbered dies interspersed and staggered with respect to even numbered dies only one of the axes. Wire bonds may be formed between the odd numbered dies, skipping the even numbered dies, and wire bonds may be formed between the even numbered dies, skipping the odd numbered dies. The long length of the bond wires increases an inductance of the wire bonds relative to parasitic capacitance of the semiconductor dies, thereby increasing signal path bandwidth of the semiconductor device.

Abstract: A semiconductor device comprises a semiconductor substrate, and a pair of metal gates extends upwards from the semiconductor substrate. First and second channel regions are disposed between inner sidewalls of the pair of metal gates. First and second drain regions are disposed between the inner sidewalls of the pair of metal gates and are disposed directly over the first and second channel regions, respectively. First and second source regions are disposed between the inner sidewalls of the pair of metal gates directly below the first and second channel regions, respectively. A capacitor dielectric structure is disposed below the first and second source regions. A bottom capacitor electrode is disposed below the capacitor dielectric. The capacitor dielectric structure separates the first and second drain regions from the bottom capacitor electrode.

Abstract: A semiconductor device of an embodiment includes a first electrode, a second electrode, a first metallic region provided between the first electrode and the second electrode and includes at least one metallic element selected from the group consisting of indium (In), gallium (Ga), zinc (Zn), aluminum (Al), magnesium (Mg), manganese (Mn), titanium (Ti), tungsten (W), molybdenum (Mo), and tin (Sn), a second metallic region provided between the first metallic region and the second electrode and includes the at least one metallic element, a semiconductor region provided between the first metallic region and the second metallic region and includes the at least one metallic element and oxygen (O), an insulating region provided between the first metallic region and the second metallic region and is surrounded by the semiconductor region, a gate electrode surrounding the semiconductor region, and a gate insulating layer provided between the semiconductor region and the gate electrode.

Abstract: A method for forming a gate structure of a 3D memory device is provided. The method comprises forming an array wafer including a periphery region and a staircase and array region. A process of forming the array wafer comprises forming an etch stop layer on a first substrate in the periphery region, forming an array device on the first substrate in the staircase and array region, and forming at least one first vertical through in the periphery region and in contact with the etch stop layer. The method further comprises forming a CMOS wafer, and bonding the array wafer and the CMOS wafer. The method further comprises forming at least one through substrate contact penetrating the first substrate and the etch stop layer, and in contact with the at least one first vertical through contact.

Abstract: A display device includes a substrate including a display area and a peripheral area outside the display area. A circuit unit is disposed in the display area and includes a semiconductor layer. An insulating layer is on the semiconductor layer. A conductive layer is connected to the semiconductor layer through a contact hole in the insulating layer. The conductive layer includes an underlayer including a metal nitride including a first metal. A display element is disposed on the circuit unit and includes a pixel electrode electrically connected to the conductive layer. A connection layer is disposed under the conductive layer. The connection layer corresponds to the contact hole and includes a second metal.

Abstract: A semiconductor memory device includes a capacitor having a bottom electrode and a top electrode, a dielectric layer between the bottom and top electrodes, and an interface layer between the top electrode and the dielectric layer, the interface layer including a metal oxide and an additional constituent at a grain boundary of the interface layer.

Abstract: A method for forming a gate structure of a 3D memory device is provided. The method comprises forming an array wafer including a periphery region and a staircase and array region. A process of forming the array wafer comprises forming an array well structure in a first substrate in the periphery region, forming an array device on the first substrate in the staircase and array region, and forming at least one vertical through contact in the periphery region and in contact with the array well structure. The method further comprises forming a CMOS wafer, and bonding the array wafer and the CMOS wafer. The method further comprises forming at least one through substrate contact penetrating the first substrate and the array well structure, and in contact with the at least one vertical through contact.

Abstract: An improved memory cell architecture including a nanostructure field-effect transistor (nano-FET) and a horizontal capacitor extending at least partially under the nano-FET and methods of forming the same are disclosed. In an embodiment, semiconductor device includes a channel structure over a semiconductor substrate; a gate structure encircling the channel structure; a first source/drain region adjacent the gate structure; and a capacitor adjacent the first source/drain region, the capacitor extending under the first source/drain region and the gate structure in a cross-sectional view.

Abstract: A display device with a narrow bezel is provided. The display device includes a pixel circuit and a driver circuit which are provided on the same plane. The driver circuit includes a selection circuit and a buffer circuit. The selection circuit includes a first transistor. The buffer circuit includes a second transistor. The first transistor has a region overlapping with the second transistor. One of a source and a drain of the first transistor is electrically connected to a gate of the second transistor. One of a source and a drain of the second transistor is electrically connected to the pixel circuit.

Abstract: Described herein are IC devices that include transistors with contacts to one of the source/drain (S/D) regions being on the front side of the transistors and contacts to the other one of the S/D regions being on the back side of the transistors (i.e., “back-side contacts”). Using transistors with one front-side and one back-side S/D contacts provides advantages and enables unique architectures that were not possible with conventional front-end-of-line transistors with both S/D contacts being on one side.

Abstract: A DRAM memory cell and memory cell array incorporating a metal silicide bit line buried within a doped portion of a semiconductor substrate and a vertical semiconductor structure electrically connected with a memory element such as a capacitive memory element. The buried metal silicide layer functions as a bit buried bit line which can provide a bit line voltage to the capacitive memory element via the vertical transistor structure. The buried metal silicide layer can be formed by allotaxy or mesotaxy. The vertical semiconductor structure can be formed by epitaxially growing a semiconductor material on an etched surface of the doped portion of the semiconductor substrate.

Abstract: A semiconductor memory device includes a stack disposed over a first substrate; an etch barrier including a plurality of dummy channels which pass through the stack and surround a coupling region; and a plurality of channels passing through the stack in a cell region outside the coupling region. The stack has a structure in which first dielectric layers and second dielectric layers are alternately stacked, inside the coupling region, and has a structure in which the first dielectric layers and electrode layers are alternately stacked, outside the coupling region.