Abstract: A semiconductor device includes an epitaxial substrate. The epitaxial substrate includes a substrate. A strain relaxed layer covers and contacts the substrate. A III-V compound stacked layer covers and contacts the strain relaxed layer. The III-V compound stacked layer is a multilayer epitaxial structure formed by aluminum nitride, aluminum gallium nitride or a combination of aluminum nitride and aluminum gallium nitride.

Abstract: According to one embodiment, a semiconductor wafer is formed with a plurality of first regions each provided with a circuit element and a second region between the first regions. The semiconductor wafer includes a first structure in which a first embedding material is embedded in a first recess extending in a first direction perpendicular to a surface of a substrate. The first structure is between edges of the first regions and a third region that is cut in the second region when the first regions are separated.

Abstract: A semiconductor device includes an epitaxial substrate. The epitaxial substrate includes a substrate. A strain relaxed layer covers and contacts the substrate. A III-V compound stacked layer covers and contacts the strain relaxed layer. The III-V compound stacked layer is a multilayer epitaxial structure formed by aluminum nitride, aluminum gallium nitride or a combination of aluminum nitride and aluminum gallium nitride.

Abstract: Provided are methods of manufacturing comprising providing a FET base structure, the FET base structure comprising a substrate, a drain and a source; and providing a channel layer on the FET base structure; and providing a first layer on the FET base structure. The first layer comprises a one-dimensional or two-dimensional material and is arranged on an upper surface of the channel layer so as to form a sensing surface of the FET. The step of providing the channel layer comprises forming the channel layer and subsequently transferring the channel layer onto the FET base structure. Alternatively or additionally, the step of providing the first layer on the FET base structure comprises forming the first layer and subsequently transferring the first layer onto the FET base structure.

Abstract: Disclosed is a substrate processing method including: a pressurizing operation of raising a process pressure from a first pressure (P1) to a second pressure (P2) that is greater than the atmospheric pressure; a depressurizing operation of lowering the process pressure from a sixth pressure (P6), which is greater than the atmospheric pressure, to a seventh pressure (P7); and an annealing operation of changing the process pressure into a preset pressure change pattern between the pressurizing operation and the depressurizing operation, under a temperature atmosphere of a second temperature (T2) higher than the room temperature. A temperature raising operation of raising a temperature atmosphere from a first temperature (T1) to the second temperature (T2) is performed from a preset temperature raising start point (t1) to a preset temperature raising end point (t2) while the pressurizing operation is performed or after the pressurizing operation is performed.

Abstract: Silicon carbide (SiC) crystalline materials and related methods are disclosed that provide SiC crystalline materials with reduced optical absorption. In certain aspects, SiC crystalline materials with reduced absorption coefficients for wavelengths of light within the visible spectrum are disclosed. Various peaks in absorption over a wavelength spectrum may be reduced in SiC crystalline materials to improve overall absorption coefficient uniformity across the visible spectrum. By providing such improvements in absorption coefficients for SiC crystalline materials, reduced reflection and transmission losses of light in corresponding devices may be realized. Related methods are disclosed that include various combinations of crystalline growth, with and without various post-growth thermal conditioning steps.

Abstract: A light emitting device includes: a base including: a first lead including: a first A surface, a first B surface opposite to the first A surface, and a first C surface located between the first A surface and the first B surface and defining at least one first protrusion, a second lead separated from the first lead, and a resin body covering the first C surface and holding the first lead and the second lead; a light emitting element disposed on the first A surface; and a protecting member disposed continuously on at least a portion of the first A surface and in at least a portion of a gap between the first protrusion and the resin body. In a cross-sectional view, the first protrusion extends from a first end portion of the first A surface at a second lead side toward the second lead.

Abstract: Package structures and methods for forming the same are provided. The method includes forming a passivation layer having an opening and forming a first seed layer in the opening. The method further includes filling the opening with a conductive layer over the first seed layer and bonding an integrated circuit die to the conductive layer over a first side of the passivation layer. The method further includes removing a portion of the first seed layer to expose a top surface of the conductive layer and to partially expose a first sidewall of the passivation layer from a second side of the passivation layer and forming a second seed layer over the top surface of the conductive layer and over the first sidewall of the passivation layer.

Abstract: In an embodiment, a device includes: a first redistribution structure including a first dielectric layer; a die adhered to a first side of the first redistribution structure; an encapsulant laterally encapsulating the die, the encapsulant being bonded to the first dielectric layer with first covalent bonds; a through via extending through the encapsulant; and first conductive connectors electrically connected to a second side of the first redistribution structure, a subset of the first conductive connectors overlapping an interface of the encapsulant and the die.

Abstract: This invention provides a conductive paste and a method for producing a TOPCon solar cell, by which a TOPCon solar cell can be produced by a simple method, and additionally, a TOPCon solar cell can be constructed with excellent conversion efficiency. Specifically, the invention provides a conductive paste for use as a back electrode for TOPCon solar cells, the conductive paste comprising aluminum-silicon alloy particles, an organic vehicle, and a glass powder, the aluminum-silicon alloy particles having a silicon concentration of 25 wt % or more and 40 wt % or less.

Abstract: A transistor structure, includes a buffer layer and a quantum well channel layer on top of the buffer layer. There is a barrier layer on top of the channel layer. There is a drain contact on a channel stack. A source contact is on a channel stack. A gate structure is located between the source contact and drain contact, comprising: an active gate portion having a bottom surface in contact with a bottom surface of the source and the drain contacts. A superconducting portion of the gate structure is in contact with, and adjacent to, an upper part of the active gate portion.

Abstract: A display apparatus includes: a substrate including a first area and a second area, the second area including a transmission area; main pixels on the first area, each of the main pixels including a first pixel electrode, a first opposite electrode, and a first intermediate layer between the first pixel electrode and the first opposite electrode; auxiliary pixels on the second area, each of the auxiliary pixels including a second pixel electrode, a second opposite electrode, and a second intermediate layer between the second pixel electrode and the second opposite electrode; and a metal pattern layer on the second area and surrounding the transmission area.

Abstract: A method for manufacturing a phase-change memory device includes providing a substrate including a plurality of bottom electrodes, patterning the substrate to form a plurality of pores in the substrate extending from a surface of the substrate to the bottom electrodes, depositing a phase-change material over the substrate, implanting one or more of a Ge, Sb and Te in the phase-change material to amorphize at least a portion of the phase-change material inside the pore, planarizing the device to exposed the surface of the substrate, and forming a plurality of top electrodes over the pores, in contact with the phase-change material.

Abstract: A semiconductor device having an improved source/drain region profile and a method for forming the same are disclosed. In an embodiment, a method includes etching one or more semiconductor fins to form one or more recesses; and forming a source/drain region in the one ore more recesses, the forming the source/drain region including epitaxially growing a first semiconductor material in the one or more recesses at a temperature of 600° C. to 800° C., the first semiconductor material including doped silicon germanium; and conformally depositing a second semiconductor material over the first semiconductor material at a temperature of 300° C. to 600° C., the second semiconductor material including doped silicon germanium and having a different composition than the first semiconductor material.

Abstract: A method for fabricating a semiconductor device includes the steps of forming a gate structure on a substrate, forming recesses adjacent to two sides of the gate structure, forming a buffer layer in the recesses, forming a first linear bulk layer on the buffer layer, forming a second linear bulk layer on the first linear bulk layer, forming a bulk layer on the second linear bulk layer, and forming a cap layer on the bulk layer.

Abstract: The present disclosure provides a display panel including a first substrate, pixels arranged on the first substrate and configured to define a display area, a second substrate facing the first substrate, an insulating layer on the first substrate and including an edge that is closer to the display area than an edge of the first substrate, a conductive layer on the insulating layer, and a sealing member between the first substrate and the second substrate and surrounding the display area.

Abstract: A structure includes an electrical device, and an active contact landed on a portion of the electrical device. The active contact includes a first body of a first material. A thermal dissipation pillar is adjacent the active contact and unlanded on but over the portion of the electrical device. The thermal dissipation pillar includes a second body of a second material having a higher thermal conductivity than the first material. The thermal dissipation pillar may be in thermal communication with a wire in a dielectric layer over the active contact and the thermal dissipation pillar. The electrical device can be any integrated circuit device that generates heat.

Abstract: A semiconductor structure includes a buffer layer, a channel layer, a barrier layer, a doped compound semiconductor layer, and a composition gradient layer. The buffer layer is disposed on a substrate, the channel layer is disposed on the buffer layer, the barrier layer is disposed on the channel layer, the doped compound semiconductor layer is disposed on the barrier layer, and the composition gradient layer is disposed between the barrier layer and the doped compound semiconductor layer. The barrier layer and the composition gradient layer include a same group III element and a same group V element, and the atomic percentage of the same group III element in the composition gradient layer is gradually increased in the direction from the barrier layer to the doped compound semiconductor layer. A high electron mobility transistor and a fabrication method thereof are also provided.

Abstract: A method includes providing a substrate having a surface such that a first hard mask layer is formed over the surface and a second hard mask layer is formed over the first hard mask layer, forming a first pattern in the second hard mask layer, where the first pattern includes a first mandrel oriented lengthwise in a first direction and a second mandrel oriented lengthwise in a second direction different from the first direction, and where the first mandrel has a top surface, a first sidewall, and a second sidewall opposite to the first sidewall, and depositing a material towards the first mandrel and the second mandrel such that a layer of the material is formed on the top surface and the first sidewall but not the second sidewall of the first mandrel.

Abstract: A semiconductor device includes an epitaxial substrate. The epitaxial substrate includes a substrate. A strain relaxed layer covers and contacts the substrate. A III-V compound stacked layer covers and contacts the strain relaxed layer. The III-V compound stacked layer is a multilayer epitaxial structure formed by aluminum nitride, aluminum gallium nitride or a combination of aluminum nitride and aluminum gallium nitride.