Patents Examined by Khaja Ahmad
  • Patent number: 11593688
    Abstract: In a computer-implemented method of assessing driving performance using route scoring, driving data indicative of operation of a vehicle while the vehicle was driven on a driving route may be received. Road infrastructure data indicative of one or more features of the driving route may also be received. A route score for the driving route may be calculated using the road infrastructure data, and a driving performance score for a driver of the vehicle may be calculated using the driving data and the route score for the driving route. Data may be sent to a client device via a network to cause the client device to display the driving performance score and/or a ranking based on the driving performance score, and/or the driving performance score may be used to determine a risk rating for the driver of the vehicle.
    Type: Grant
    Filed: September 17, 2020
    Date of Patent: February 28, 2023
    Inventors: Brian Mark Fields, J. Lynn Wilson
  • Patent number: 11594626
    Abstract: Structures for a bidirectional switch and methods of forming such structures. A substrate contact is formed in a trench defined in a substrate. A substrate includes a trench and a substrate contact in the trench. A bidirectional switch, which is on the substrate, includes a first source/drain electrode, a second source/drain electrode, an extension region between the first source/drain electrode and the second source/drain electrode, and a gate structure. A substrate-bias switch, which is on the substrate, includes a gate structure, a first source/drain electrode coupled to the substrate contact, a second source/drain electrode coupled to the first source/drain electrode of the bidirectional switch, and an extension region laterally between the gate structure and the first source/drain electrode.
    Type: Grant
    Filed: February 5, 2021
    Date of Patent: February 28, 2023
    Assignee: GlobalFoundries U.S. Inc.
    Inventor: Francois Hebert
  • Patent number: 11594448
    Abstract: Embodiments disclosed herein include semiconductor devices and methods of forming such semiconductor devices. In an embodiment, a method of fabricating a semiconductor device comprises, forming a first grating of parallel first lines, forming a second grating of parallel second lines, wherein the second lines are substantially orthogonal to the first lines, and wherein the first lines and second lines define a plurality of first openings, disposing a conformal mask layer over the first lines and the second lines, wherein the conformal mask layer partially fills the first openings and defines a second opening within each of the first openings, disposing a hardmask over the conformal mask layer, wherein the hardmask fills the second openings, patterning third openings into the hardmask, wherein the third openings clear the hardmask from at least one of the second openings, and removing the mask layer proximate to cleared second openings to clear first openings.
    Type: Grant
    Filed: June 7, 2019
    Date of Patent: February 28, 2023
    Assignee: Intel Corporation
    Inventors: Leonard P. Guler, Chul-Hyun Lim, Paul A. Nyhus, Elliot N. Tan, Charles H. Wallace
  • Patent number: 11587914
    Abstract: A light emitting chip including a first LED sub-unit, a second LED sub-unit disposed on the first LED sub-unit, a third LED sub-unit disposed on the second LED sub-unit, a passivation layer disposed on the third LED sub-unit, and a first connection electrode electrically connected to at least one of the first, second, and third LED sub-units, in which the first connection electrode and the third LED sub-unit form a first angle defined between an upper surface of the third LED sub-unit and an inner surface of the first connection electrode that is less than about 80°.
    Type: Grant
    Filed: April 19, 2020
    Date of Patent: February 21, 2023
    Assignee: Seoul Viosys Co., Ltd.
    Inventors: Jong Min Jang, Chang Yeon Kim, Myoung Hak Yang
  • Patent number: 11569487
    Abstract: Provided are a display device, a mask assembly, and an apparatus and a method for manufacturing the display device. The mask assembly includes: a mask frame; at least two mask sheets installed on the mask frame, each of the mask sheets including a plurality of openings; and at least two thin shielding plates installed on the mask frame such that the thin shielding plates are spaced apart from each other and shield a portion of the plurality of openings of each mask sheet, wherein one of the mask sheets and the thin shielding plates includes a shielding portion between the thin shielding plates spaced apart from each other, the shielding portion selectively blocking at least portions of the openings so as to form a deposition region having a shape other than a rectangle or a square.
    Type: Grant
    Filed: October 5, 2020
    Date of Patent: January 31, 2023
    Inventors: Jaemin Hong, Hanul Kwen, Jeunghoon Kim, Jakyung Yu, Sujin Lee
  • Patent number: 11569297
    Abstract: An image sensor includes an array of readout circuits in non-organic technology and photodiodes made of organic materials.
    Type: Grant
    Filed: November 16, 2018
    Date of Patent: January 31, 2023
    Assignee: ISORG
    Inventors: Benjamin Bouthinon, Emeline Saracco, Jean-Yves Gomez, Olivier Dhez
  • Patent number: 11568299
    Abstract: Superconducting tunnel junctions for use in, for instance, quantum processors. In one example, a quantum processor can have at least one qubit structure. The at least one qubit structure includes a first aluminum layer, a second aluminum layer, and a crystalline dielectric layer disposed between the first aluminum layer and the second aluminum layer. The crystalline dielectric layer includes a spinel crystal structure.
    Type: Grant
    Filed: July 13, 2020
    Date of Patent: January 31, 2023
    Assignee: GOOGLE LLC
    Inventor: David Kirtland Fork
  • Patent number: 11569090
    Abstract: A method of depositing a material on one of two, but not both, sidewalls of a raised structure formed on a substrate includes tilting a normal of the substrate away from a source of the deposition material or tilting the source of the deposition material away from the normal of the substrate. The method may be implemented by a plasma-enhanced chemical vapor deposition (PECVD) technique.
    Type: Grant
    Filed: July 26, 2021
    Date of Patent: January 31, 2023
    Inventors: Shih-Chun Huang, Ya-Wen Yeh, Chien-Wen Lai, Wei-Liang Lin, Ya Hui Chang, Yung-Sung Yen, Ru-Gun Liu, Chin-Hsiang Lin, Yu-Tien Shen
  • Patent number: 11563088
    Abstract: A semiconductor device includes an epitaxial substrate. The epitaxial substrate includes a substrate. A strain relaxed layer covers and contacts the substrate. A III-V compound stacked layer covers and contacts the strain relaxed layer. The III-V compound stacked layer is a multilayer epitaxial structure formed by aluminum nitride, aluminum gallium nitride or a combination of aluminum nitride and aluminum gallium nitride.
    Type: Grant
    Filed: December 10, 2019
    Date of Patent: January 24, 2023
    Inventors: Yu-Ming Hsu, Yu-Chi Wang, Yen-Hsing Chen, Tsung-Mu Yang, Yu-Ren Wang
  • Patent number: 11550072
    Abstract: A non-blended dataset related to a same surveyed area as a blended dataset is used to deblend the blended dataset. The non-blended dataset may be used to calculate a model dataset emulating the blended dataset, or may be transformed in a model domain and used to derive sparseness weights, model domain masking, scaling or shaping functions used to deblend the blended dataset.
    Type: Grant
    Filed: August 5, 2021
    Date of Patent: January 10, 2023
    Assignee: CGG SERVICES SAS
    Inventors: Gordon Poole, Henning Hoeber, Adel Khalil
  • Patent number: 11551923
    Abstract: A Taiko wafer ring cut process method is provided. The Taiko wafer ring cut process method includes the following steps. A Taiko wafer is disposed on the platform. The Taiko wafer is performing by laser ring cutting so that a Taiko ring and an edge portion of the Taiko wafer are separated from a wafer portion of the Taiko wafer. The wafer portion of the Taiko wafer is adhered to a frame.
    Type: Grant
    Filed: January 15, 2021
    Date of Patent: January 10, 2023
    Inventors: Chien-Hsiung Huang, Chao-Tsung Tsou, Cheng-Yen Lin
  • Patent number: 11552189
    Abstract: Embodiments are directed to high electron mobility transistor (HEMT) devices and methods. One such HEMT device includes a substrate having a first surface, and first and second heterostructures on the substrate and facing each other. Each of the first and second heterostructures includes a first semiconductor layer on the first surface of the substrate, a second semiconductor layer on the first surface of the substrate, and a two-dimensional electrode gas (2DEG) layer between the first and second semiconductor layers. A doped semiconductor layer is disposed between the first and second heterostructures, and a source contact is disposed on the first heterostructure and the second heterostructure.
    Type: Grant
    Filed: September 21, 2020
    Date of Patent: January 10, 2023
    Assignee: STMicroelectronics S.r.l.
    Inventor: Davide Giuseppe Patti
  • Patent number: 11532739
    Abstract: An integrated enhancement/depletion mode high electron mobility transistor (HEMT) includes a substrate, a buffer layer, a first barrier layer, a second barrier layer, a first source, a first drain a first gate, a second source, a second drain, and a second gate. The buffer layer is on the substrate. The first barrier layer is on the buffer layer, and the second barrier layer is on the first barrier layer. The second barrier layer covers a portion of the first barrier layer. The first source, the first drain, and the first gate are on the first barrier layer, and the second source, the second drain, and the second gate are on the second banner layer.
    Type: Grant
    Filed: August 4, 2020
    Date of Patent: December 20, 2022
    Inventors: Xianfeng Ni, Qian Fan, Wei He
  • Patent number: 11531872
    Abstract: The present disclosure relates to a novel neuron circuit using a p-n-p-n diode to realize small size and low power consumption. The neuron circuit according to one embodiment of the present disclosure may generate potential by charging current input from synapses through a capacitor. In this case, when the generated potential exceeds a critical value, the neuron circuit may generate and output a spike voltage corresponding to the generated potential using a p-n-p-n diode connected to the capacitor.
    Type: Grant
    Filed: June 9, 2020
    Date of Patent: December 20, 2022
    Assignee: Korea University Research and Business Foundation
    Inventors: Sang Sig Kim, Kyoung Ah Cho, Young Soo Park, Doo Hyeok Lim, Sol A Woo
  • Patent number: 11532564
    Abstract: Package structures and methods for forming the same are provided. The package structure includes an integrated circuit die and a package layer surrounding the integrated circuit die. The package structure also includes a redistribution structure over the package layer and electrically connected to the integrated circuit die. The redistribution structure includes a passivation layer and a conductive layer formed in the passivation layer. The integrated circuit die further includes a connector formed over the conductive layer and covered a top surface of the passivation layer. In addition, a bottom surface of the connector and a top surface of the connector are both wider than a neck portion of the connector.
    Type: Grant
    Filed: December 14, 2020
    Date of Patent: December 20, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Da Tsai, Cheng-Ping Lin, Wei-Hung Lin, Chih-Wei Lin, Ming-Da Cheng, Ching-Hua Hsieh, Chung-Shi Liu
  • Patent number: 11527574
    Abstract: A method for fabricating stacked resistive memory with individual switch control is provided. The method includes forming a first random access memory (ReRAM) device. The method further includes forming a second ReRAM device in a stacked nanosheet configuration on the first ReRAM device. The method also includes forming separate gate contacts for the first ReRAM device and the second ReRAM device.
    Type: Grant
    Filed: April 14, 2021
    Date of Patent: December 13, 2022
    Inventors: Takashi Ando, Jingyun Zhang, Pouya Hashemi, Alexander Reznicek, Choonghyun Lee
  • Patent number: 11522159
    Abstract: A protection film for a window of a display device is capable of preventing or substantially preventing damage to a securing unit of the window. A protection film for a window of a display device includes: a protection layer; and a barrier wall on the protection layer, the protection layer having a groove at an edge of the protection layer.
    Type: Grant
    Filed: July 15, 2019
    Date of Patent: December 6, 2022
    Assignee: Samsung Display Co., Ltd.
    Inventors: Soonsung Park, Jeongjin Kim, Jooil Kim, Dohyeon Kim
  • Patent number: 11521965
    Abstract: Junction field effect transistors (JFETs) and related manufacturing methods are disclosed herein. A disclosed four terminal JFET includes an integrated high voltage capacitor (HVC). The JFET includes a first terminal coupled to a drain region, a second terminal coupled to the source region, a third terminal coupled to the base region, and an integrated HVC terminal coupled to an integrated HVC electrode which forms an HVC with the drain region. The JFET also includes a channel formed by a channel region. A bias on the base region fully depletes the channel of majority carriers. The channel has an unbiased concentration of majority carriers. The integrated HVC electrode is positioned relative to the channel region such that applying the bias to the integrated HVC terminal depletes the channel by at most ten percent of the unbiased concentration of majority carriers.
    Type: Grant
    Filed: April 23, 2021
    Date of Patent: December 6, 2022
    Assignee: Monolithic Power Systems, Inc.
    Inventor: Vipindas Pala
  • Patent number: 11514303
    Abstract: Synaptic resistors (synstors), and their method of manufacture and integration into exemplary circuits are provided. Synstors are configured to emulate the analog signal processing, learning, and memory functions of synapses. Circuits incorporating synstors are capable of performing signal processing and learning concurrently in parallel analog mode with speed, energy efficiency, and functions superior to computers.
    Type: Grant
    Filed: January 24, 2019
    Date of Patent: November 29, 2022
    Assignee: The Regents of the University of California
    Inventor: Yong Chen
  • Patent number: 11515410
    Abstract: A Group III-V semiconductor structure having a semiconductor device. The semiconductor device has a source and drain recess regions extending through a barrier layer and into a channel layer. A regrown, doped Group III-V ohmic contact layer is disposed on and in direct contact with the source and drain recess regions. A gate electrode is disposed in a gap in the regrown, doped Group III-V ohmic contact layer and on the barrier layer A dielectric structure is disposed over the ohmic contact layer and over the barrier layer and extending continuously from a region over the source recess region to one side of the stem to portion and then extending continuously from an opposite side of the stem portion to a region over the drain recess region, a portion of the dielectric structure being in contact with the stem portion and the barrier layer.
    Type: Grant
    Filed: October 30, 2020
    Date of Patent: November 29, 2022
    Assignee: Raytheon Company
    Inventors: Jeffrey R. LaRoche, Kelly P. Ip, Thomas E. Kazior, Eduardo M. Chumbes