Abstract: A microelectromechanical systems (MEMS) device comprises a MEMS die that comprises first and second diaphragms, a first plurality of electrodes each disposed on the first diaphragm, and a second plurality of electrodes each disposed on the second diaphragm. A fixed dielectric element is disposed between the first and second diaphragms and includes a plurality of apertures. The MEMS die further comprises a third plurality of electrodes, wherein each of the third plurality comprises a first conductive layer disposed on the first diaphragm proximate to at least one of the first plurality and a second conductive layer disposed on the second diaphragm proximate to at least one of the second plurality, and a conductive pin that extends through an aperture of the plurality of apertures and electrically connects the first conductive layer to the second conductive layer.

Abstract: A semiconductor device includes a Schottky diode on a silicon-on-insulator (SOI) substrate. The Schottky diode includes a guard ring with a first guard ring segment contacting a barrier region on a first lateral side of the barrier region, and a second guard ring segment contacting the barrier region on a second, opposite, lateral side of the barrier region. The first and second guard ring segments extend deeper in the semiconductor layer than the barrier region. The Schottky diode further includes a drift region contacting the barrier region, and may include a buried layer having the same conductivity type as the barrier region, extending at least partway under the drift region. The barrier region is isolated from the substrate dielectric layer of the SOI substrate by an isolation region having the same conductivity type as the guard ring. A metal containing layer is formed on the barrier region.

Abstract: Provided are a nitride semiconductor device and a manufacturing method thereof. The nitride semiconductor device includes a substrate, a first nitride semiconductor layer, a second nitride semiconductor layer, a first metal layer, a second metal layer and a dielectric layer. The first nitride semiconductor layer is disposed on the substrate. The second nitride semiconductor layer is disposed on the first nitride semiconductor layer. The first metal layer is disposed in the second nitride semiconductor layer. The second metal layer is disposed on the second nitride semiconductor layer. The dielectric layer is disposed between the first metal layer and the second nitride semiconductor layer and/or between the second metal layer and the second nitride semiconductor layer.

Abstract: A light emitting device including a board, a first stacked structure configured to emit light having a first wavelength, a second stacked structure configured to emit light having a second wavelength, a third stacked structure configured to emit light having a third wavelength, a first connection electrode electrically connected to the first stacked structure, the second stacked structure, and the third stacked structure, and a protection material covering at least a portion of the first connection electrode, in which each of the first, second, and third stacked structures is configured to selectively emit light while being connected to the first connection electrode, and the protection material is configured to transmit at least 50% of light having the first wavelength, light having the second wavelength, and light having the third wavelength upon operation of each of the first, second, and third stacked structures.

Abstract: A semiconductor device including an element isolation in a trench formed in an upper surface of a semiconductor substrate, a trench isolation including a void in a trench directly under the element isolation, and a Cu wire with Cu ball connected to a pad on the semiconductor substrate, is formed. The semiconductor device has a circular trench isolation arrangement prohibition region that overlaps the end portion of the Cu ball in plan view, and the trench isolation is separated from the trench isolation arrangement prohibition region in plan view.

Abstract: A vertical semiconductor device includes a substrate, a drift region over the substrate, an upper region on the drift region, a top surface over the upper region and being substantially planar, and a series of implants of a second dopant in the upper region, such that each implant of the series of implants is located at a different depth below the top surface. The series of implants forms at least two gate region. The substrate and the drift region are doped with a first dopant of a first polarity. The second dopant has a second polarity opposite that of the first polarity. At least a portion of a channel region is provided between the at least two gate regions, and a conducting gap is defined within the channel region and between opposing sidewalls of the at least two gate regions.

Abstract: A device includes a buried oxide layer disposed on a substrate, a first region disposed on the buried oxide layer and a first ring region disposed in the first region. The first ring region includes a portion of a guardring. The device further includes a first terminal region disposed in the first ring region, a second ring region disposed in the first region and a second terminal region disposed in the second ring region. The first terminal region is connected to an anode and the second terminal region is connected to a cathode. The first region has a graded doping concentration. The first region, the second ring region and the second terminal region have a first conductivity type, and the first ring region and the first terminal region have a second conductivity type. The first conductivity type is different from the second conductivity type.

Abstract: A method for manufacturing a light-emitting element includes: providing a structure body including: a semiconductor structure body having a first surface, a second surface located on a side opposite to the first surface, and a lateral surface that connects the first surface and the second surface, a first insulating film covering the lateral surface of the semiconductor structure body, a second insulation film covering the first surface of the semiconductor structure body and an upper surface of the first insulating film on a first surface side, and a substrate facing the second surface of the semiconductor structure body; forming a mask on a part of the second insulating film located above the first surface of the semiconductor structure body; and removing a part of the second insulating film located around the mask in a top view and exposed from the mask.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to devices with a metal field plate extension and methods of manufacture. The structure includes: a gate structure over a semiconductor substrate; a drift region under the gate structure; a source region adjacent to the gate structure; a drain region in the drift region; a isolation structure within the drift region; and a contact extending from the source region and into the isolation structure within the drift region.

Abstract: A semiconductor device includes a semiconductor layer including a super junction layer in which an n-type pillar layer and a p-type pillar layer are alternately disposed and a p-type withstand voltage holding structure formed on an upper layer part of the semiconductor layer to surround an active region. At least one withstand voltage holding structure overlaps with the super junction layer in a plan view. At least one withstand voltage holding structure overlapping with the super junction layer in a plan view has a gap which is an intermittent part of the withstand voltage holding structure.

Abstract: In a computer-implemented method of assessing driving performance using route scoring, driving data indicative of operation of a vehicle while the vehicle was driven on a driving route may be received. Road infrastructure data indicative of one or more features of the driving route may also be received. A route score for the driving route may be calculated using the road infrastructure data, and a driving performance score for a driver of the vehicle may be calculated using the driving data and the route score for the driving route. Data may be sent to a client device via a network to cause the client device to display the driving performance score and/or a ranking based on the driving performance score, and/or the driving performance score may be used to determine a risk rating for the driver of the vehicle.

Abstract: The present application provides a method for avoiding a damage to an overlay metrology mark, forming a plurality of raised silicon structures on an active area of a scribe line area on a silicon substrate, forming first to third dielectric layers on the silicon structure, and forming an axial structure of a fin and a spacer on the first to third dielectric layers; forming a shallow trench isolation (STI) area on the silicon substrate between the axial structures; removing a portion of the silicon structure along the height thereof on the scribe line area, the height of the residual silicon structure is 150-300 angstroms higher than that of the STI area; forming a plurality of dummy gates on the residual silicon structure on the scribe line, then applying a dielectric layer to fill a gap between the dummy gates, polishing the dielectric layer to expose the top of the dummy gate.

Abstract: Semiconductor devices and methods of forming a semiconductor device that includes a polysilicon layer that may improve device reliability and/or a functioning of the device. An example device may include a wide band-gap semiconductor layer structure including a drift region that has a first conductivity type; a plurality of gate trenches in an upper portion of the semiconductor layer structure, each gate trench having a bottom surface, a first sidewall, a second sidewall, and an upper opening; and a plurality of polysilicon layers, each polysilicon layer on the second sidewall of a respective gate trench.

Abstract: In some embodiments, a semiconductor structure includes: a first epitaxial oxide semiconductor layer; a metal layer; and a contact layer adjacent to the metal layer, and between the first epitaxial oxide semiconductor layer and the metal layer. The contact layer can include an epitaxial oxide semiconductor material. The contact layer can also include a region comprising a gradient in a composition of the epitaxial oxide semiconductor material adjacent to the metal layer, or a gradient in a strain of the epitaxial oxide semiconductor material over a region adjacent to the metal layer.

Abstract: A semiconductor nanoparticle includes a core and a shell covering a surface of the core. The shell has a larger bandgap energy than the core and is in heterojunction with the core. The semiconductor nanoparticle emits light when irradiated with light. The core is made of a semiconductor that contains M1, M2, and Z. M1 is at least one element selected from the group consisting of Ag, Cu, and Au. M2 is at least one element selected from the group consisting of Al, Ga, In and Tl. Z is at least one element selected from the group consisting of S, Se, and Te. The shell is made of a semiconductor that consists essentially of a Group 13 element and a Group 16 element.

Abstract: A semiconductor structure includes a plurality of memory cells stacked up along a first direction. Each of the memory cells include a memory stack, connecting lines, and insulating layers. The memory stack includes a first dielectric layer, a channel layer disposed on the first dielectric layer, a charge trapping layer disposed on the channel layer, a second dielectric layer disposed on the charge trapping layer, and a gate layer disposed in between the channel layer and the second dielectric layer. The connecting lines are extending along the first direction and covering side surfaces of the memory stack. The insulating layers are extending along the first direction, wherein the insulating layers are located aside the connecting lines and covering the side surfaces of the memory stack.

Abstract: A microelectromechanical system includes a backplate and a diaphragm. The backplate includes spaced stator elements with voids formed therebetween. The stator element includes a first conductive element. The diaphragm includes a plurality of corrugations facing the voids respectively. Each corrugation includes a groove formed at a surface thereof away from the backplate. The corrugation includes a second conductive element. The diaphragm is moveable with respect to the backplate in response to a pressure exerted thereon to cause the corrugations to be moved into or out of the corresponding voids, thereby changing the capacitance formed between the first and second conductive elements. The corrugations are defined by grooves formed at surfaces away from the backplate, which facilitate to control the compliance of the diaphragm and reduce stiffness of the diaphragm. The corrugation can be formed with lower aspect ratios, which allows it to be formed using standard front side processes.

Abstract: A memory device includes a package substrate and at least one stack of a plurality of semiconductor dies disposed on the package substrate. The plurality of semiconductor dies can be stacked in a shingled configuration. Each semiconductor die includes a plurality of slits disposed in a first direction. An offset direction defining the shingled arrangement is in-line with the first direction. Each semiconductor die can include a die substrate and a plurality of memory planes disposed on the die substrate with each memory plane having a memory cell array. Each slit can divide and separate each memory plane into at least one of logic blocks or sub-logic blocks. The semiconductor die can include a plurality of bond pads linearly aligned in a second direction that is perpendicular to the first direction.

Abstract: A first light-emitting element and a second light-emitting element that have a resonance structure that causes output light from a light-emission functional layer to resonate between a reflective layer and a semi-transmissive reflective layer, and a pixel definition layer, and in which an aperture part is formed to correspond to each of the first light-emitting element and the second light-emitting element, are formed on a base. A first interval between the reflective layer and the semi-transmissive reflective layer in the first light-emitting element and a second interval between the reflective layer and the semi-transmissive reflective layer in the second light-emitting element are different, and a film thickness of the pixel definition layer is less than a difference between the first interval and the second interval.

Abstract: A semiconductor device, including: a drift layer of a first conductivity type provided in a semiconductor base; a base layer of a second conductivity type provided in the semiconductor base at a front surface side thereof; a plurality of first trenches provided in the semiconductor base at a front surface side thereof, and having a plurality of first portions extending in a first direction to form a striped pattern; a second trench provided in the semiconductor base at a front surface side thereof, and having a plurality of second portions extending parallel to the first portions; a plurality of gate electrodes respectively provided in the first trenches; and a diode electrode provided in the second trench. The diode electrode includes: a plurality of inner electrodes provided in the second portions, and an outer electrode connecting the inner electrodes and surrounding ends of the first portions in a plan view.