Patents Examined by Khaja Ahmad
  • Patent number: 11183461
    Abstract: A method of manufacturing a semiconductor structure includes following operations. A first die is provided. A first molding is formed to encapsulate the first die. A second die is disposed over the first molding. A mold chase is disposed over the second die and the first molding. The mold chase includes a protrusion protruded from the mold chase towards the first molding. A molding material is disposed between the mold chase and the first molding. A second molding is formed to surround the second die. The second die is at least partially covered by the second molding. The disposing of the mold chase includes surrounding the protrusion of the mold chase by the molding material.
    Type: Grant
    Filed: January 7, 2020
    Date of Patent: November 23, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chen-Hua Yu, Kai-Chiang Wu, Chun-Lin Lu
  • Patent number: 11183544
    Abstract: The invention discloses a display panel and a display device. The display panel includes a display area, wherein the display area includes an image capturing area and a non-image capturing area surrounding the image capturing area, and the display area further includes: a plurality of light emitting units distributed in the image capturing area and the non-image capturing area; and a plurality of pixel circuit units, each of the pixel circuit units respectively connected to a corresponding one of the light emitting units, wherein each of the pixel circuit units is disposed in the non-image capturing area.
    Type: Grant
    Filed: September 19, 2019
    Date of Patent: November 23, 2021
    Assignee: WUHAN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventor: Feng Zhang
  • Patent number: 11183568
    Abstract: Disclosures of the present invention mainly describe a two-dimensional semiconductor device (TDSD), comprising: a two-dimensional semiconductor material (TDSM) layer, a superacid action layer and a superacid solution. The TDSM layer is made of a transition-metal dichalcogenide, and the superacid action layer is formed on the TDSM layer. Particularly, an oxide material is adopted for making the superacid action layer, such that the superacid solution is subsequently applied to the superacid action layer so as to make the superacid solution gets into the superacid action layer by diffusion effect. Experimental data have proved that, letting the superacid solution diffuse into the superacid action layer can not only apply a chemical treatment to the TDSM layer, but also make the TDSD have a luminosity enhancement. Particularly, the luminosity enhancement would not be reduced even if the TDSD contacts with water and/or organic solution during other subsequent manufacturing processes.
    Type: Grant
    Filed: October 9, 2019
    Date of Patent: November 23, 2021
    Assignee: National Tsing Hua University
    Inventors: I-Tung Chen, Ying-Yu Lai, Chun-An Chen, Xin-Quan Zhang, Yi-Hsien Lee
  • Patent number: 11183469
    Abstract: A semiconductor device according to the present embedment includes a substrate having a first region provided with a semiconductor element and a second region provided from the first region to an end. A material film is provided above the first and second regions. A first metal film is provided on the material film in the second region or on the material film between the first region and the second region. A trench, which caves in toward the substrate from a surface of the material film in the first region and from a surface of the material film under the first metal film, is provided in the material film between the first metal film and the first region.
    Type: Grant
    Filed: February 14, 2020
    Date of Patent: November 23, 2021
    Assignee: Kioxia Corporation
    Inventors: Yusuke Akada, Rina Kadowaki, Hiroyuki Maeda
  • Patent number: 11171209
    Abstract: A semiconductor device having an improved source/drain region profile and a method for forming the same are disclosed. In an embodiment, a method includes etching one or more semiconductor fins to form one or more recesses; and forming a source/drain region in the one ore more recesses, the forming the source/drain region including epitaxially growing a first semiconductor material in the one or more recesses at a temperature of 600° C. to 800° C., the first semiconductor material including doped silicon germanium; and conformally depositing a second semiconductor material over the first semiconductor material at a temperature of 300° C. to 600° C., the second semiconductor material including doped silicon germanium and having a different composition than the first semiconductor material.
    Type: Grant
    Filed: August 22, 2019
    Date of Patent: November 9, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Heng-Wen Ting, Kei-Wei Chen, Chii-Horng Li, Pei-Ren Jeng, Hsueh-Chang Sung, Yen-Ru Lee, Chun-An Lin
  • Patent number: 11171043
    Abstract: Methods and architectures for IC interconnect trenches, and trench plugs that define separations between two adjacent trench ends. Plugs and trenches may be defined through a multiple patterning process. An upper grating pattern may be summed with a plug keep pattern into a pattern accumulation layer. The pattern accumulation layer may be employed to define plug masks. A lower grating pattern may then be summed with the plug masks to define a pattern in trench ILD material, which can then be backfilled with interconnect metallization. As such, a complex damascene interconnect structure can be fabricated at the scaled-down geometries achievable with pitch-splitting techniques. In some embodiments, the trenches are located at spaces between first spacer masks defined in a patterning process associated with the first grating pattern while the plug masks are located based on a tone-inversion of second spacer masks associated with the second grating pattern.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: November 9, 2021
    Assignee: Intel Corporation
    Inventors: Charles H. Wallace, Marvin Y. Paik, Hyunsoo Park, Mohit K. Haran, Alexander F. Kaplan, Ruth A. Brain
  • Patent number: 11171264
    Abstract: A light emitting module including a base substrate, a first light emitting diode disposed on the base substrate, and a second light emitting diode disposed on the base substrate and spaced apart from the first light emitting diode, in which each of the first light emitting diode and the second light emitting diode includes a first light emitting region and a second light emitting region, the second light emitting region being spaced apart from the first light emitting region and surrounding the first light emitting region.
    Type: Grant
    Filed: March 19, 2018
    Date of Patent: November 9, 2021
    Assignee: Seoul Semiconductor Co., Ltd.
    Inventors: Jong Min Lee, Bang Hyun Kim, Jae Ho Lee
  • Patent number: 11171058
    Abstract: Techniques are disclosed for customization of fin-based transistor devices to provide a diverse range of channel configurations and/or material systems within the same integrated circuit die. In accordance with one example embodiment, sacrificial fins are removed and replaced with custom semiconductor material of arbitrary composition and strain suitable for a given application. In one such case, each of a first set of the sacrificial fins is recessed or otherwise removed and replaced with a p-type material, and each of a second set of the sacrificial fins is recessed or otherwise removed and replaced with an n-type material. The p-type material can be completely independent of the process for the n-type material, and vice-versa. Numerous other circuit configurations and device variations are enabled using the techniques provided herein.
    Type: Grant
    Filed: August 3, 2017
    Date of Patent: November 9, 2021
    Assignee: Intel Corporation
    Inventors: Glenn A. Glass, Daniel B. Aubertine, Anand S. Murthy, Gaurav Thareja, Tahir Ghani
  • Patent number: 11171062
    Abstract: A semiconductor structure and a method for forming same, the forming method including: providing a base, where the base includes a substrate and a fin protruding from the substrate, an isolation layer is formed on the substrate exposed by the fin, and the isolation layer covers a part of side walls of the fin; forming a dummy gate structure across the fin, including a dummy gate layer, where the dummy gate structure covers a part of the top and a part of the side walls of the fin; forming an interlayer dielectric layer on the substrate exposed by the dummy gate structure, where the interlayer dielectric layer exposes the top of the dummy gate structure; removing the dummy gate layer and forming an opening in the interlayer dielectric layer; removing partial thickness of the isolation layer exposed by the opening and forming a groove in the isolation layer; and forming a gate structure in the groove and the opening, where the gate structure crosses the fin and covers a part of the top and a part of the side wa
    Type: Grant
    Filed: October 15, 2019
    Date of Patent: November 9, 2021
    Assignees: Semiconductor Manufacturing International (Beijing) Corporation, Semiconductor Manufacturing International (Shanghai) Corporation
    Inventors: Nan Wang, Zhan Ying
  • Patent number: 11171236
    Abstract: A method includes forming a first semiconductor fin and a second semiconductor fin parallel to each other and protruding higher than top surfaces of isolation regions. The isolation regions include a portion between the first and the second semiconductor fins. The method further includes forming a gate stack crossing over the first and the second semiconductor fins, etching a portion of the gate stack to form an opening, wherein the portion of the isolation regions, the first semiconductor fin, and the second semiconductor fin are exposed to the opening, etching the first semiconductor fin, the second semiconductor fin, and the portion of the isolation regions to extend the opening into a bulk portion of a semiconductor substrate below the isolation regions, and filling the opening with a dielectric material to form a cut-fin isolation region.
    Type: Grant
    Filed: October 5, 2018
    Date of Patent: November 9, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shiang-Bau Wang, Li-Wei Yin, Shao-Hua Hsu
  • Patent number: 11171313
    Abstract: Display panel stack-up structures are described. In an embodiment, a display panel includes a substrate, a light source, and a multiple layer thin film encapsulation over the light source. In an embodiment, the display panel additionally includes an anti-reflection layer over the light source. In an embodiment, an incoherence layer is located within the thin film encapsulation.
    Type: Grant
    Filed: June 21, 2019
    Date of Patent: November 9, 2021
    Assignee: Apple Inc.
    Inventors: Yifan Zhang, Amin Salehi, Yun Liu, Paul S. Drzaic, Tae-Wook Koh, Chih Jen Yang, Bhadrinarayana Lalgudi Visweswaran, Chieh-Wei Chen
  • Patent number: 11162024
    Abstract: A semiconductor nanoparticle includes a core and a shell covering a surface of the core. The shell has a larger bandgap energy than the core and is in heterojunction with the core. The semiconductor nanoparticle emits light when irradiated with light. The core is made of a semiconductor that contains M1, M2, and Z. M1 is at least one element selected from the group consisting of Ag, Cu, and Au. M2 is at least one element selected from the group consisting of Al, Ga, In and Tl. Z is at least one element selected from the group consisting of S, Se, and Te. The shell is made of a semiconductor that consists essentially of a Group 13 element and a Group 16 element.
    Type: Grant
    Filed: January 2, 2020
    Date of Patent: November 2, 2021
    Assignees: OSAKA UNIVERSITY, National University Corporation Tokai National Higher Education and Research System, NICHIA CORPORATION
    Inventors: Susumu Kuwabata, Taro Uematsu, Kazutaka Wajima, Tsukasa Torimoto, Tatsuya Kameyama, Daisuke Oyamatsu, Kenta Niki
  • Patent number: 11164937
    Abstract: A semiconductor device includes a semiconductor substrate, a capacitor, and an interconnection layer. The capacitor is over the semiconductor substrate and includes a bottom electrode, a top electrode, and an insulator layer. The top electrode has a top surface and a bottom surface rougher than the top surface of the top electrode. The insulator layer is between the bottom electrode and the top electrode. The interconnection layer is over the semiconductor substrate and is electrically connected to the capacitor.
    Type: Grant
    Filed: January 23, 2019
    Date of Patent: November 2, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Chen Ho, Chien Lin, You-Hua Chou, Hsing-Yuan Huang, Cheng-Yu Hung
  • Patent number: 11164830
    Abstract: Various embodiments provide a semiconductor chip, wherein the semiconductor chip comprises a first contact area and a second contact area both formed at a frontside of the semiconductor chip; a passivation layer arranged at the frontside between the first contact area and the second contact area; and a contact stack formed over the frontside of the semiconductor chip and comprising a plurality of layers, wherein at least one layer of the plurality of layers is removed from the passivation layer and boundary regions of the contact areas being adjacent to the passivation layer and wherein at least one another layer of the plurality of different layer is present in the boundary region of the contact areas adjoining the passivation layer.
    Type: Grant
    Filed: October 7, 2018
    Date of Patent: November 2, 2021
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Dietrich Bonart, Ludger Borucki, Martina Debie, Bernhard Weidgans
  • Patent number: 11158701
    Abstract: Provided is a memcapacitor. The memcapacitor includes: a first electrode having a metal-doped perovskite composition; a second electrode disposed on the first electrode; and a dielectric thin film having a perovskite composition, disposed between the first electrode and the second electrode, and having a variable dielectric constant depending on a voltage between the first electrode and the second electrode.
    Type: Grant
    Filed: November 22, 2019
    Date of Patent: October 26, 2021
    Assignee: Gwangju Institute of Science and Technology
    Inventors: Sanghan Lee, Hyunji An, Jiwoong Yang
  • Patent number: 11158827
    Abstract: An IR organic photoelectric device having a simplified device structure may include an anode and a cathode facing each other and an infrared absorption and hole transport composite monolayer between the anode and the cathode. An organic image sensor including the IR organic photoelectric device may include an absorption layer between the infrared absorption and hole transport composite monolayer and the cathode.
    Type: Grant
    Filed: May 24, 2019
    Date of Patent: October 26, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong-Seok Leem, Gae Hwang Lee, Sung Young Yun, Kwang Hee Lee, Yong Wan Jin
  • Patent number: 11158646
    Abstract: A memory device with a dielectric blocking layer for improving interpoly dielectric breakdown is provided. Embodiments include.
    Type: Grant
    Filed: January 14, 2019
    Date of Patent: October 26, 2021
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventor: Soh Yun Siah
  • Patent number: 11152471
    Abstract: Semiconductor devices including a first region having a first three Nitride (III-N) layer and a second III-N layer, the second III-N layer is over the first III-N. The second III-N layer has spontaneous polarization less than the first III-N layer, such that a two-dimensional hole gas (2-DHG) will be formed at a junction of the first III-N layer to the second III-N layer. An Anode forms an ohmic contact to the 2-DHG. A second region includes a third III-N layer and a forth III-N layer, such that the fourth III-N layer is over the third III-N. The forth III-N layer has spontaneous polarization greater than the third III-N layer, such that two-dimensional electron gas (2-DEG) will be formed at a junction of the third III-N layer to the forth III-N layer. A Cathode forms an ohmic contact to the 2-DEG. The first and second regions are connected at an interface.
    Type: Grant
    Filed: March 26, 2020
    Date of Patent: October 19, 2021
    Assignee: Mitsubishi Electric Research Laboratories, Inc.
    Inventors: Koon Hoo Teo, Nadim Chowdhury
  • Patent number: 11152569
    Abstract: A memory device includes a substrate; a bottom electrode disposed over the substrate; an insulating layer disposed over the bottom electrode, the insulating layer having a through hole defined in the insulating layer; a heater disposed in the through hole; a phase change material layer disposed over the heater; a selector layer disposed over the phase change material layer; and a metal layer disposed over the selector layer. The metal layer is wider than the phase change material layer.
    Type: Grant
    Filed: January 31, 2018
    Date of Patent: October 19, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Jau-Yi Wu
  • Patent number: 11145662
    Abstract: A memory structure including a substrate, a first transistor, a second transistor, and a trench capacitor is provided. The trench capacitor is disposed in the substrate and is connected between the first transistor and the second transistor.
    Type: Grant
    Filed: July 31, 2020
    Date of Patent: October 12, 2021
    Assignee: Powerchip Semiconductor Manufacturing Corporation
    Inventor: Shun-Hao Chao