Patents Examined by Khaja Ahmad
  • Patent number: 10319675
    Abstract: The present disclosure provides one embodiment of a semiconductor structure that includes an interconnection structure formed on a semiconductor substrate; and a capacitor disposed in the interconnection structure. The interconnection structure includes a top electrode; a bottom electrode; a dielectric material layer sandwiched between the top and bottom electrodes; and a nanocrystal layer embedded in the dielectric material layer.
    Type: Grant
    Filed: January 13, 2016
    Date of Patent: June 11, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Cheng-Chieh Lai, Meng-Ting Yu, Yung-Hsien Wu, Kuang-Hsin Chen
  • Patent number: 10304763
    Abstract: A method for producing wafer level packaging using an embedded leadframe strip and the resulting device are provided. Embodiments include placing dies into a mold with an active side of each die facing a surface of the mold; placing a leadframe strip on the mold, wherein the leadframe strip includes etched and half etched portions positioned between each die; placing a mold cover over the mold and dies; and adding mold compound in spaces between the dies and mold cover.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: May 28, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Richard S. Graf, Sudeep Mandal, Kibby Horsford
  • Patent number: 10304915
    Abstract: The present application discloses a method of fabricating a display substrate. The method includes forming a sacrificial layer including a plurality of sacrificial blocks on a base substrate; forming a pixel definition material layer on the base substrate subsequent to forming the sacrificial layer; and removing the sacrificial layer thereby forming a pixel definition layer comprising a plurality of pixel definition blocks. Each of the plurality of sacrificial blocks is formed to have a first side surface distal to the base substrate, a second side surface facing the first side surface and proximal to the base substrate, and a third side surface connecting the first side surface and the second side surface. An average tangential inclination of the third side surface with respect to the second side surface is an acute angle.
    Type: Grant
    Filed: April 17, 2017
    Date of Patent: May 28, 2019
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventor: Dejiang Zhao
  • Patent number: 10294770
    Abstract: Systems and methods for automated workflow capture in a drilling application are provided. The interactions between a user and the drilling application are automatically tracked via a graphical user interface (GUI) of the drilling application executable at a computing device. The tracked interactions are based in part on input received from the user via the GUI with respect to a user-initiated operation related to an activity at a well site. Data for the workflow is captured based on the tracked interactions. The captured workflow data is stored in a memory of the computing device.
    Type: Grant
    Filed: October 6, 2014
    Date of Patent: May 21, 2019
    Assignee: LANDMARK GRAPHICS CORPORATION
    Inventors: Florin M. Anghelescu, David Crawshay
  • Patent number: 10290588
    Abstract: In one implementation, a method for forming ultra-thin semiconductor components includes fabricating multiple devices including a first device and a second device in a semiconductor wafer, and forming a street trench within the semiconductor wafer and between the first and second devices. The method continues with forming a dielectric skeleton structure over the semiconductor wafer, the dielectric skeleton structure laterally extending to at least partially cover the first and second devices, while also substantially filling the street trench. The method continues with thinning the semiconductor wafer from a backside to expose the dielectric skeleton structure in the street trench to form a first ultra-thin semiconductor component having the first device, and a second ultra-thin semiconductor component having the second device. The method can conclude with cutting through the dielectric skeleton structure to singulate the first and second ultra-thin semiconductor components.
    Type: Grant
    Filed: June 7, 2016
    Date of Patent: May 14, 2019
    Assignee: Infineon Technologies Americas Corp.
    Inventor: Robert Montgomery
  • Patent number: 10290551
    Abstract: The present invention provides an overlay mark, including a substrate and plural sets of first pattern block and second pattern block. A first direction and a second direction are defined on the substrate, wherein the first direction and the second direction are perpendicular to each other. In each set, the first pattern block is rotational symmetrical to the second pattern block. Each first pattern block includes a big frame and plural small frame. Each second pattern block includes a big frame and plural small frame. The width of the big frame is greater than three times of the width of the small frame. The present invention further provides a method for evaluating the stability of a semiconductor manufacturing process.
    Type: Grant
    Filed: April 24, 2017
    Date of Patent: May 14, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: En-Chiuan Liou, Yu-Cheng Tung
  • Patent number: 10269706
    Abstract: A semiconductor device includes a first interlayer dielectric (ILD) layer disposed over a substrate, and a first metal wiring pattern formed in the first interlayer dielectric layer and extending in a first direction parallel with the substrate. In a cross section along a second direction which crosses the first direction and is in parallel with the substrate, a top of the first metal wiring pattern is covered by a first two-dimensional material layer.
    Type: Grant
    Filed: July 26, 2016
    Date of Patent: April 23, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ming-Han Lee, Shau-Lin Shue
  • Patent number: 10262907
    Abstract: Embodiments of the invention include a dye and pry process for removing quad flat no-lead (QFN) packages and bottom termination components (BTC) from card assemblies. Aspects of the invention include immersing a semiconductor package assembly in a solution comprising dye and placing the immersed semiconductor package assembly under vacuum pressure. Vacuum conditions ensure that the dye solution is pulled into any cracks in the solder formed between the semiconductor package assembly and the QFN package or BTC. The package assembly is dried and a hole is drilled to expose a bottom surface of the QFN package or BTC. The QFN package or BTC is then removed by applying a force to the exposed bottom surface. The semiconductor package assembly can then be inspected for the dye to locate cracks.
    Type: Grant
    Filed: November 21, 2017
    Date of Patent: April 16, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Tim A. Bartsch, Jennifer Bennett, James D. Bielick, David J. Braun, John R. Dangler, Stephen M. Hugo, Theron L. Lewis, Timothy P. Younger
  • Patent number: 10256293
    Abstract: A structure such as an integrated circuit device is described having a line of material with critical dimensions which vary within a distribution substantially less than that of a mask element, such as a patterned resist element, used in manufacturing the line of material.
    Type: Grant
    Filed: September 7, 2017
    Date of Patent: April 9, 2019
    Assignee: Synopsys, Inc.
    Inventors: Victor Moroz, Lars Bomholt
  • Patent number: 10224367
    Abstract: The present invention is directed to a memory device that includes an array of memory cells. Each of the memory cells includes a memory element connected to a two-terminal selector element. The two-terminal selector element includes a first electrode and a second electrode with a switching layer interposed therebetween. The switching layer includes a plurality of metal-rich clusters embedded in a nominally insulating matrix. One or more conductive paths are formed in the switching layer when an applied voltage to the memory cell exceeds a threshold level. Each of the memory cells may further include an intermediate electrode interposed between the memory element and the two-terminal selector element. The two-terminal selector element may further include a third electrode formed between the first electrode and the switching layer, and a fourth electrode formed between the second electrode and the switching layer.
    Type: Grant
    Filed: May 18, 2016
    Date of Patent: March 5, 2019
    Assignee: Avalanche Technology, Inc.
    Inventors: Hongxin Yang, Kimihiro Satoh, Xiaobin Wang
  • Patent number: 10211044
    Abstract: This method for manufacturing a ferroelectric thin film device includes: a lower electrode film formation step of forming a lower electrode film on a substrate; a ferroelectric thin film formation step of forming a ferroelectric thin film made of a sodium potassium niobate on the lower electrode film; an upper electrode film formation step of forming an upper electrode film on the ferroelectric thin film; and an upper electrode film etching step of shaping the upper electrode film into a desired micro-pattern by performing a reactive ion etching process on the upper electrode film. The upper electrode film etching step is a step of calculating a rate of change of sodium emission intensity in an ion plasma generated by the reactive ion etching process and determining that the etching process is completed when the rate of change falls below a predetermined threshold.
    Type: Grant
    Filed: March 2, 2016
    Date of Patent: February 19, 2019
    Assignee: SUMITOMO CHEMICAL COMPANY, LIMITED
    Inventors: Fumimasa Horikiri, Kenji Shibata, Kazutoshi Watanabe, Kazufumi Suenaga
  • Patent number: 10211192
    Abstract: [Object] To suppress appearance of a ghost. [Solving Means] The present optical module includes a sensor configured to pick up an image of an image pickup object, and a memory chip configured to store pixel data read out from the sensor and having the sensor joined thereto. The memory chip is connected to a substrate by a connection portion by flip-chip connection. The sensor can be connected by a wire to the memory chip, to which the sensor is joined. Further, the sensor can be joined to the memory chip in such a manner as to project toward an opening of the substrate. The present technology can be applied to a camera module.
    Type: Grant
    Filed: January 25, 2017
    Date of Patent: February 19, 2019
    Assignee: SONY CORPORATION
    Inventors: Toshiaki Iwafuchi, Takayuki Ezaki, Tomoshi Oode
  • Patent number: 10199218
    Abstract: A Ga source gas and a nitrogen source gas are supplied to form a GaN channel layer on a semiconductor substrate. Next, a temperature is lowered while supplying at least the nitrogen source gas. Next, the Ga source gas is not supplied and an Al source gas and the nitrogen source gas are supplied. Next, the temperature is raised while not supplying the Al source gas and the Ga source gas and supplying the nitrogen source gas. Next, the Al source gas and the nitrogen source gas are supplied and at least one of the Ga source gas and an In source gas is supplied to form a AlxGayInzN barrier layer (x+y+z=1, x>0, y?0, z?0, y+z>0).
    Type: Grant
    Filed: July 24, 2017
    Date of Patent: February 5, 2019
    Assignee: Mitsubishi Electric Corporation
    Inventors: Atsushi Era, Susumu Hatakenaka
  • Patent number: 10192782
    Abstract: A method of manufacturing the semiconductor device includes providing a first interlayer dielectric layer having a conductive pattern, sequentially forming a first etch stop layer, a second etch stop layer, a second interlayer dielectric layer and a mask pattern on the first interlayer dielectric layer, forming an opening in the second interlayer dielectric layer using the mask pattern as a mask, the opening exposing the second etch stop layer, and performing an etching process including simultaneously removing the mask pattern and the second etch stop layer exposed by the opening to expose the first etch stop layer.
    Type: Grant
    Filed: June 23, 2015
    Date of Patent: January 29, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Woojin Lee, VietHa Nguyen, Wookyung You, Doo-Sung Yun, Hyunbae Lee, Byunghee Kim, Sang Hoon Ahn, Seungyong Yoo, Naein Lee, Hoyun Jeon
  • Patent number: 10181487
    Abstract: Implementations of semiconductor packages may include: a substrate coupled to one or more die and to one or more connectors, a glass lid coupled over one or more die by an adhesive and a housing comprising one or more sides and a bottom opening and a top opening. The substrate may be coupled to the housing at the bottom opening and the glass lid may be coupled under the housing at the top opening.
    Type: Grant
    Filed: August 17, 2017
    Date of Patent: January 15, 2019
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Yu-Te Hsieh
  • Patent number: 10181407
    Abstract: This method for manufacturing a niobate-system ferroelectric thin-film device includes: a lower electrode film formation step of forming a lower electrode film on a substrate; a ferroelectric thin film formation step of forming a niobate-system ferroelectric thin film on the lower electrode film; an etch mask pattern formation step of forming an etch mask in a desired pattern on the niobate-system ferroelectric thin film, the etch mask being an amorphous fluororesin film laminated via a noble metal film; and a ferroelectric thin film etching step of shaping the niobate-system ferroelectric thin film into a desired fine pattern by wet etching using an etchant comprising: a chelating agent; an aqueous alkaline solution containing an aqueous ammonia solution; and an aqueous hydrogen peroxide solution.
    Type: Grant
    Filed: March 17, 2016
    Date of Patent: January 15, 2019
    Assignee: SUMITOMO CHEMICAL COMPANY, LIMITED
    Inventors: Fumimasa Horikiri, Kenji Shibata, Kazutoshi Watanabe, Kazufumi Suenaga, Masaki Noguchi, Kenji Kuroiwa
  • Patent number: 10179878
    Abstract: For a metal gate replacement integration scheme, the present disclosure describes removing a polysilicon gate electrode with a highly selective wet etch chemistry without damaging surrounding layers. For example, the wet etch chemistry can include one or more alkaline solvents with a steric hindrance amine structure, a buffer system that includes tetramethylammonium hydroxide (TMAH) and monoethanolamine (MEA), one or more polar solvents, and water.
    Type: Grant
    Filed: July 24, 2017
    Date of Patent: January 15, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Neng-Jye Yang, Kuo Bin Huang, Ming-Hsi Yeh, Shun Wu Lin, Yu-Wen Wang, Jian-Jou Lian, Shih Min Chang
  • Patent number: 10181559
    Abstract: There is provided an workpiece etching method executed in manufacturing a magneto-resistive effect element, the workpiece including first and second multilayer films, the first multilayer film including first and second magnetic layers and a tunnel barrier layer formed between the first and second magnetic layers, and the second multilayer film being a multilayer film constituting a pinning layer in the magneto-resistive effect element. The method includes: etching the first multilayer film; generating plasma of a first gas including hydrocarbon and noble gases inside a chamber of a plasma processing apparatus to etch the second multilayer film inside the chamber; and generating plasma of a second gas including gas containing carbon and oxygen, an oxygen gas and a noble gas and not containing hydrogen inside the chamber to remove a carbon-containing deposit formed on the workpiece in the generating the plasma of the first gas.
    Type: Grant
    Filed: December 14, 2017
    Date of Patent: January 15, 2019
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Takuya Kubo, Song yun Kang
  • Patent number: 10177292
    Abstract: A light emitting device may comprise a wing portion of an electrode exposed from the resin housing. The wing portion may be made by a single or multiple stamp cutting process. To increase the connecting region between the electrode and solder, the outer side surface of the wing portion is an uneven surface. The device may further comprise a protective plating layer and an external protective plating layer. The protective plating layer may be coated on the top surface, bottom surface and a portion of the side surface of the electrode. The external portative plating layer would be coated on the outer surface of the wing region. The light reflection of the device from top surface of the electrode portion can be maintained and the outer side surface of wing portion can be protected for improving the reliability of connection between light emitting device and outer substrate.
    Type: Grant
    Filed: March 27, 2017
    Date of Patent: January 8, 2019
    Assignee: EVERLIGHT ELECTRONICS CO., LTD.
    Inventors: Chung-Chuan Hsieh, Yung Chieh Chen
  • Patent number: 10176998
    Abstract: A semiconductor device includes a substrate, a dielectric layer and a floating gate. The dielectric layer disposed on the substrate. The floating gate disposed on the dielectric layer. After a first programming process, the floating gate is configured to store first electrons that are to be combined with ions from the dielectric layer. After a second programming process, the floating gate is configured to store second electrons, and a number of the second electrons is larger than a number of the first electrons.
    Type: Grant
    Filed: April 25, 2017
    Date of Patent: January 8, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-Yu Wu, Meng-Chun Shih, Chin-Huang Wang