Patents Examined by Khaja Ahmad
  • Patent number: 12009414
    Abstract: A transistor structure, includes a buffer layer and a quantum well channel layer on top of the buffer layer. There is a barrier layer on top of the channel layer. There is a drain contact on a channel stack. A source contact is on a channel stack. A gate structure is located between the source contact and drain contact, comprising: an active gate portion having a bottom surface in contact with a bottom surface of the source and the drain contacts. A superconducting portion of the gate structure is in contact with, and adjacent to, an upper part of the active gate portion.
    Type: Grant
    Filed: December 3, 2021
    Date of Patent: June 11, 2024
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Eunjung Cha, Cezar Bogdan Zota
  • Patent number: 12004434
    Abstract: A method for manufacturing a phase-change memory device includes providing a substrate including a plurality of bottom electrodes, patterning the substrate to form a plurality of pores in the substrate extending from a surface of the substrate to the bottom electrodes, depositing a phase-change material over the substrate, implanting one or more of a Ge, Sb and Te in the phase-change material to amorphize at least a portion of the phase-change material inside the pore, planarizing the device to exposed the surface of the substrate, and forming a plurality of top electrodes over the pores, in contact with the phase-change material.
    Type: Grant
    Filed: November 2, 2020
    Date of Patent: June 4, 2024
    Assignee: International Business Machines Corporation
    Inventors: Praneet Adusumilli, Matthew Joseph BrightSky, Guy M. Cohen, Robert L. Bruce
  • Patent number: 12004386
    Abstract: A display apparatus includes: a substrate including a first area and a second area, the second area including a transmission area; main pixels on the first area, each of the main pixels including a first pixel electrode, a first opposite electrode, and a first intermediate layer between the first pixel electrode and the first opposite electrode; auxiliary pixels on the second area, each of the auxiliary pixels including a second pixel electrode, a second opposite electrode, and a second intermediate layer between the second pixel electrode and the second opposite electrode; and a metal pattern layer on the second area and surrounding the transmission area.
    Type: Grant
    Filed: July 7, 2020
    Date of Patent: June 4, 2024
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Jongwon Chae, Moosoon Ko, Sunghoon Moon, Sewan Son, Yongje Jeon, Jingoo Jung
  • Patent number: 12002854
    Abstract: A semiconductor device having an improved source/drain region profile and a method for forming the same are disclosed. In an embodiment, a method includes etching one or more semiconductor fins to form one or more recesses; and forming a source/drain region in the one ore more recesses, the forming the source/drain region including epitaxially growing a first semiconductor material in the one or more recesses at a temperature of 600° C. to 800° C., the first semiconductor material including doped silicon germanium; and conformally depositing a second semiconductor material over the first semiconductor material at a temperature of 300° C. to 600° C., the second semiconductor material including doped silicon germanium and having a different composition than the first semiconductor material.
    Type: Grant
    Filed: November 8, 2021
    Date of Patent: June 4, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Heng-Wen Ting, Kei-Wei Chen, Chii-Horng Li, Pei-Ren Jeng, Hsueh-Chang Sung, Yen-Ru Lee, Chun-An Lin
  • Patent number: 11990547
    Abstract: A method for fabricating a semiconductor device includes the steps of forming a gate structure on a substrate, forming recesses adjacent to two sides of the gate structure, forming a buffer layer in the recesses, forming a first linear bulk layer on the buffer layer, forming a second linear bulk layer on the first linear bulk layer, forming a bulk layer on the second linear bulk layer, and forming a cap layer on the bulk layer.
    Type: Grant
    Filed: September 27, 2020
    Date of Patent: May 21, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chun-Yu Chen, Bo-Lin Huang, Jhong-Yi Huang, Keng-Jen Lin, Yu-Shu Lin
  • Patent number: 11972999
    Abstract: A structure includes an electrical device, and an active contact landed on a portion of the electrical device. The active contact includes a first body of a first material. A thermal dissipation pillar is adjacent the active contact and unlanded on but over the portion of the electrical device. The thermal dissipation pillar includes a second body of a second material having a higher thermal conductivity than the first material. The thermal dissipation pillar may be in thermal communication with a wire in a dielectric layer over the active contact and the thermal dissipation pillar. The electrical device can be any integrated circuit device that generates heat.
    Type: Grant
    Filed: December 7, 2021
    Date of Patent: April 30, 2024
    Assignee: GlobalFoundries U.S. Inc.
    Inventors: Mark D. Levy, Rajendran Krishnasamy, Michael J. Zierak, Siva P. Adusumilli
  • Patent number: 11974450
    Abstract: The present disclosure provides a display panel including a first substrate, pixels arranged on the first substrate and configured to define a display area, a second substrate facing the first substrate, an insulating layer on the first substrate and including an edge that is closer to the display area than an edge of the first substrate, a conductive layer on the insulating layer, and a sealing member between the first substrate and the second substrate and surrounding the display area.
    Type: Grant
    Filed: December 29, 2020
    Date of Patent: April 30, 2024
    Assignee: Samsung Display Co., Ltd.
    Inventors: Seungjae Lee, Hyesoo Jee, Wongeun Lee, Hansoo Kim, Kyungmin Park
  • Patent number: 11967642
    Abstract: A semiconductor structure includes a buffer layer, a channel layer, a barrier layer, a doped compound semiconductor layer, and a composition gradient layer. The buffer layer is disposed on a substrate, the channel layer is disposed on the buffer layer, the barrier layer is disposed on the channel layer, the doped compound semiconductor layer is disposed on the barrier layer, and the composition gradient layer is disposed between the barrier layer and the doped compound semiconductor layer. The barrier layer and the composition gradient layer include a same group III element and a same group V element, and the atomic percentage of the same group III element in the composition gradient layer is gradually increased in the direction from the barrier layer to the doped compound semiconductor layer. A high electron mobility transistor and a fabrication method thereof are also provided.
    Type: Grant
    Filed: September 3, 2021
    Date of Patent: April 23, 2024
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Chih-Yen Chen, Tuan-Wei Wang, Franky Juanda Lumbantoruan, Chun-Yang Chen
  • Patent number: 11955338
    Abstract: A method includes providing a substrate having a surface such that a first hard mask layer is formed over the surface and a second hard mask layer is formed over the first hard mask layer, forming a first pattern in the second hard mask layer, where the first pattern includes a first mandrel oriented lengthwise in a first direction and a second mandrel oriented lengthwise in a second direction different from the first direction, and where the first mandrel has a top surface, a first sidewall, and a second sidewall opposite to the first sidewall, and depositing a material towards the first mandrel and the second mandrel such that a layer of the material is formed on the top surface and the first sidewall but not the second sidewall of the first mandrel.
    Type: Grant
    Filed: January 30, 2023
    Date of Patent: April 9, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shih-Chun Huang, Ya-Wen Yeh, Chien-Wen Lai, Wei-Liang Lin, Ya Hui Chang, Yung-Sung Yen, Ru-Gun Liu, Chin-Hsiang Lin, Yu-Tien Shen
  • Patent number: 11955519
    Abstract: A semiconductor device includes an epitaxial substrate. The epitaxial substrate includes a substrate. A strain relaxed layer covers and contacts the substrate. A III-V compound stacked layer covers and contacts the strain relaxed layer. The III-V compound stacked layer is a multilayer epitaxial structure formed by aluminum nitride, aluminum gallium nitride or a combination of aluminum nitride and aluminum gallium nitride.
    Type: Grant
    Filed: April 17, 2023
    Date of Patent: April 9, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yu-Ming Hsu, Yu-Chi Wang, Yen-Hsing Chen, Tsung-Mu Yang, Yu-Ren Wang
  • Patent number: 11949012
    Abstract: A semiconductor device including: a first transistor which include a first gate stack on a substrate; and a second transistor which includes a second gate stack on the substrate, wherein the first gate stack includes a first ferroelectric material layer disposed on the substrate, a first work function layer disposed on the first ferroelectric material layer and a first upper gate electrode disposed on the first work function layer, wherein the second gate stack includes a second ferroelectric material layer disposed on the substrate, a second work function layer disposed on the second ferroelectric material layer and a second upper gate electrode disposed on the second work function layer, wherein the first work function layer includes the same material as the second work function layer, and wherein an effective work function of the first gate stack is different from an effective work function of the second gate stack.
    Type: Grant
    Filed: December 8, 2020
    Date of Patent: April 2, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jong Ho Park, Wan Don Kim, Weon Hong Kim, Hyeon Jun Baek, Byoung Hoon Lee, Jeong Hyuk Yim, Sang Jin Hyun
  • Patent number: 11942337
    Abstract: The apparatus includes a support unit to support the substrate in a treatment space of a process chamber, a first fluid supply unit to supply a supercritical fluid having an organic solvent dissolved in the supercritical fluid, to the treatment space, a second fluid supply unit to supply the supercritical fluid having no organic solvent dissolved in the supercritical fluid, to the treatment space, an exhaust unit to exhaust the treatment space, a controller to control the first fluid supply unit, the second fluid supply unit, and the exhaust unit. The controller controls the first and second fluid supply units such that the supercritical fluid having no organic solvent dissolved in the supercritical fluid is supplied to the treatment space through the second fluid supply unit, after the supercritical fluid mixed with the organic solvent is supplied to the treatment space through the first fluid supply unit.
    Type: Grant
    Filed: October 6, 2020
    Date of Patent: March 26, 2024
    Assignee: SEMES CO., LTD.
    Inventors: Eui Sang Lim, Young Hun Lee, Jinwoo Jung, Miso Park, Byongwook Ahn, Yong Hee Lee
  • Patent number: 11942416
    Abstract: Embodiments disclosed herein include electronic systems with vias that include a horizontal and vertical portion in order to provide interconnects to stacked components, and methods of forming such systems. In an embodiment, an electronic system comprises a board, a package substrate electrically coupled to the board, and a die electrically coupled to the package substrate. In an embodiment the die comprises a stack of components, and a via adjacent to the stack of components, wherein the via comprises a vertical portion and a horizontal portion.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: March 26, 2024
    Assignee: Intel Corporation
    Inventors: Ehren Mannebach, Aaron Lilak, Hui Jae Yoo, Patrick Morrow, Anh Phan, Willy Rachmady, Cheng-Ying Huang, Gilbert Dewey, Rishabh Mehandru
  • Patent number: 11942419
    Abstract: An integrated circuit structure includes a dielectric layer and an etch stop layer. The etch stop layer includes a first sub layer including a metal nitride over the first dielectric layer, and a second sub layer overlying or underlying the first sub layer. The second sub layer includes a metal compound comprising an element selected from carbon and oxygen, and is in contact with the first sub layer.
    Type: Grant
    Filed: June 30, 2022
    Date of Patent: March 26, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shiu-Ko JangJian, Tsung-Hsuan Hong, Chun Che Lin, Chih-Nan Wu
  • Patent number: 11935946
    Abstract: Structures for a silicon-controlled rectifier and methods of forming a structure for a silicon-controlled rectifier. The structure comprises a semiconductor substrate, a dielectric layer on the semiconductor substrate, and a first well and a second well in the semiconductor substrate beneath the dielectric layer. The first well has a first conductivity type, the second well has a second conductivity type opposite to the first conductivity type, and the second well adjoins the first well along a p-n junction. The structure further comprises a first terminal and a second terminal above the dielectric layer, a first connection extending through the dielectric layer from the first terminal to the first well, and a second connection extending through the dielectric layer from the second terminal to the second well.
    Type: Grant
    Filed: June 27, 2022
    Date of Patent: March 19, 2024
    Assignee: GlobalFoundries U.S. Inc.
    Inventors: Shesh Mani Pandey, Souvick Mitra, Anindya Nath
  • Patent number: 11935915
    Abstract: Provided is a memcapacitor. The memcapacitor includes: a first electrode having a metal-doped perovskite composition; a second electrode disposed on the first electrode; and a dielectric thin film having a perovskite composition, disposed between the first electrode and the second electrode, and having a variable dielectric constant depending on a voltage between the first electrode and the second electrode.
    Type: Grant
    Filed: August 19, 2021
    Date of Patent: March 19, 2024
    Assignee: Gwangji Institute of Science and Technology
    Inventors: Sanghan Lee, Hyunji An, Jiwoong Yang
  • Patent number: 11937443
    Abstract: The present disclosure provides a display panel including a first substrate, pixels arranged on the first substrate and configured to define a display area, a second substrate facing the first substrate, an insulating layer on the first substrate and including an edge that is closer to the display area than an edge of the first substrate, a conductive layer on the insulating layer, and a sealing member between the first substrate and the second substrate and surrounding the display area.
    Type: Grant
    Filed: December 29, 2020
    Date of Patent: March 19, 2024
    Assignee: Samsung Display Co., Ltd.
    Inventors: Seungjae Lee, Hyesoo Jee, Wongeun Lee, Hansoo Kim, Kyungmin Park
  • Patent number: 11929415
    Abstract: A device is disclosed. The device includes a source contact and a drain contact, a first dielectric between the source contact and the drain contact, a channel under the source contact and the drain contact, and a gate electrode below the channel, the gate electrode in an area under the first dielectric that does not laterally extend under the source contact or the drain contact. A second dielectric is above the gate electrode and underneath the channel.
    Type: Grant
    Filed: June 20, 2019
    Date of Patent: March 12, 2024
    Assignee: Intel Corporation
    Inventors: Chieh-Jen Ku, Pei-Hua Wang, Bernhard Sell, Travis W. Lajoie
  • Patent number: 11929430
    Abstract: A method includes providing a semiconductor body including a plurality of two-dimensional charge carrier gas channels, forming a gate fin by forming a pair of gate trenches in an upper surface of the semiconductor body, the pair of gate trenches exposing each one of two-dimensional charge carrier gas channels, providing source and drain contacts that are electrically connected to each one of the plurality of two-dimensional charge carrier gas channels, providing a gate structure that is configured to control a conductive connection between the source and drain contacts, wherein providing the gate structure includes forming a layer of doped type III-nitride semiconductor material that covers the gate fin and extends into the gate trenches, and forming a conductive gate electrode on top of the layer of doped type III-nitride semiconductor material.
    Type: Grant
    Filed: December 28, 2021
    Date of Patent: March 12, 2024
    Assignee: Infineon Technologies Austria AG
    Inventors: Thomas Detzel, Gerhard Prechtl, Oliver Haeberlen
  • Patent number: 11923463
    Abstract: This disclosure provides a diode including a semiconductor region having at least one two-dimensional carrier channel of a first conductivity type. The diode also includes a plurality of sidewalls exposed in the semiconductor region defining at least one trench extending through the at least one two-dimensional carrier channel and a material of a second conductivity type, the second conductivity type being the other of the n-type and the p-type conductivity, disposed on the plurality of sidewalls and in contact with the at least one two-dimensional carrier channel. The diode also includes an anode material in contact with at least a portion of the semiconductor region and in contact with at least a portion of the material of the second conductivity type, and a cathode material in contact with the at least one two-dimensional carrier channel.
    Type: Grant
    Filed: April 29, 2021
    Date of Patent: March 5, 2024
    Assignee: Virginia Tech Intellectual Properties, Inc.
    Inventors: Yuhao Zhang, Ming Xiao