Patents Examined by Khaja Ahmad
  • Patent number: 10707401
    Abstract: A technique relates to forming a sidewall tunnel junction. A first conducting layer is formed using a first shadow mask evaporation. A second conducting layer is formed on a portion of the first conducting layer, where the second conducting layer is formed using a second shadow mask evaporation. An oxide layer is formed on the first conducting layer and the second conducting layer. A third conducting layer is formed on part of the oxide layer, such that the sidewall tunnel junction is positioned between the first conducting layer and the third conducting layer.
    Type: Grant
    Filed: April 17, 2019
    Date of Patent: July 7, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Markus Brink, Sami Rosenblatt
  • Patent number: 10698994
    Abstract: A device package includes a sensor die, one or more additional dies adjacent the sensor die, and a molding compound encircling the sensor die and the one or more additional dies. The device package further includes redistribution layers over the sensor die, the one or more additional dies, and the molding compound. The redistribution layers include first conductive features in a first dielectric layer. The first conductive features electrically connect the sensor die to the one or more additional dies. The redistribution layers further include an array of electrodes in a second dielectric layer over the first dielectric layer and electrically connected to the sensor die.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: June 30, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Chih Huang, Chih-Hsuan Tai, Yu-Jen Cheng, Chih-Hua Chen, Yu-Feng Chen, Hao-Yi Tsai, Chung-Shi Liu, Chen-Hua Yu
  • Patent number: 10700276
    Abstract: The present invention discloses a preparation method of a Cu-based resistive random access memory, and a memory. The preparation method includes: performing composition and a chemical combination treatment on a lower copper electrode (10) to generate a compound buffer layer (40), wherein the compound buffer layer (40) is capable of preventing the oxidation of the lower copper electrode (10); depositing a solid electrolyte material (50) on the compound buffer layer (40); and depositing an upper electrode (60) on the solid electrolyte material (50) to form the memory.
    Type: Grant
    Filed: April 22, 2016
    Date of Patent: June 30, 2020
    Assignee: THE INSTITUTE OF MICROELECTRONICS OF CHINESE ACADEMY OF SCIENCES
    Inventors: Hangbing Lv, Ming Liu, Qi Liu, Shibing Long
  • Patent number: 10686036
    Abstract: A method of making a bipolar transistor includes patterning a first photoresist over a collector region of the bipolar transistor, the first photoresist defining a first opening. The method further includes performing a first implantation process through the first opening. The method further includes patterning a second photoresist over the collector region, the second photoresist defining a second opening different from the first opening. The method further includes performing a second implantation process through the second opening, wherein a dopant concentration resulting from the second implantation process is different from a dopant concentration resulting from the first implantation process.
    Type: Grant
    Filed: May 4, 2017
    Date of Patent: June 16, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Fu-Hsiung Yang, Long-Shih Lin, Kun-Ming Huang, Chih-Heng Shen, Po-Tao Chu
  • Patent number: 10676668
    Abstract: For a metal gate replacement integration scheme, the present disclosure describes removing a polysilicon gate electrode with a highly selective wet etch chemistry without damaging surrounding layers. For example, the wet etch chemistry can include one or more alkaline solvents with a steric hindrance amine structure, a buffer system that includes tetramethylammonium hydroxide (TMAH) and monoethanolamine (MEA), one or more polar solvents, and water.
    Type: Grant
    Filed: December 14, 2018
    Date of Patent: June 9, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Neng-Jye Yang, Kuo Bin Huang, Ming-Hsi Yeh, Shun Wu Lin, Yu-Wen Wang, Jian-Jou Lian, Shih Min Chang
  • Patent number: 10679897
    Abstract: Disclosed herein is a device wafer processing method including a protective film forming step of applying a water-soluble protective film material to the front side of a device wafer having devices separated by division lines and next exposing the division lines to form a protective film for protecting each device, an application time recording step of recording the time at which the water-soluble protective film material is applied to the device wafer, a determining step of determining whether or not a predetermined duration has elapsed from the time recorded in the application time recording step, an etching step of dry-etching the device wafer along the division lines after performing the determining step, and a protective film removing step of supplying a cleaning water to the protective film to thereby remove the protective film after performing the etching step. Only when it is determined in the determining step that the predetermined duration has not elapsed, the etching step is performed.
    Type: Grant
    Filed: November 21, 2017
    Date of Patent: June 9, 2020
    Assignee: DISCO CORPORATION
    Inventors: Koichi Shigematsu, Satoshi Kumazawa
  • Patent number: 10672850
    Abstract: A display unit with which lowering of long-term reliability of a transistor is decreased is provided. The display unit includes a display section having a plurality of organic EL devices with light emitting color different from each other and a plurality of pixel circuits that are singly provided for every said organic EL device for every pixel. The pixel circuit has a first transistor for writing a video signal, a second transistor for driving the organic EL device based on the video signal written by the first transistor, and a retentive capacity, and out of the first transistor and the second transistor, a third transistor provided correspondingly to a second organic EL device adjacent to a first organic EL device is arranged farther from the first organic EL device than a first retentive capacity provided correspondingly to the second organic EL device out of the retentive capacity.
    Type: Grant
    Filed: October 25, 2018
    Date of Patent: June 2, 2020
    Assignee: Sony Corporation
    Inventors: Takayuki Taneda, Tetsuro Yamamoto, Katsuhide Uchino
  • Patent number: 10665452
    Abstract: A method for improving source/drain performance through conformal solid state doping and its resulting device are disclosed. Specifically, the doping takes place through an atomic layer deposition of a dopant layer. Embodiments of the invention may allow for an increased doping layer, improved conformality, and reduced defect formation, in comparison to alternate doping methods, such as ion implantation or epitaxial doping.
    Type: Grant
    Filed: June 26, 2018
    Date of Patent: May 26, 2020
    Assignee: ASM IP Holdings B.V.
    Inventors: Qi Xie, David de Roest, Jacob Woodruff, Michael Eugene Givens, Jan Willem Maes, Timothee Blanquart
  • Patent number: 10665775
    Abstract: There is disclosed an information storage element including a first layer including a ferromagnetic layer with a magnetization direction perpendicular to a film face; an insulation layer coupled to the first layer; and a second layer coupled to the insulation layer opposite the first layer, the second layer including a fixed magnetization so as to be capable of serving as a reference of the first layer. The first layer is capable of storing information according to a magnetization state of a magnetic material, and the magnetization state is configured to be changed by a spin injection. A magnitude of an effective diamagnetic field which the first layer receives is smaller than a saturated magnetization amount of the first layer.
    Type: Grant
    Filed: October 22, 2018
    Date of Patent: May 26, 2020
    Assignee: Sony Corporation
    Inventors: Kazutaka Yamane, Masanori Hosomi, Hiroyuki Ohmori, Kazuhiro Bessho, Yutaka Higo, Hiroyuki Uchida, Tetsuya Asayama
  • Patent number: 10665652
    Abstract: An organic light-emitting display apparatus includes: a first substrate; an insulating layer on the first substrate; a signal wiring on the insulating layer; an organic light-emitting device on the first substrate, the organic light-emitting device defining an active area and including a first electrode, a second electrode, and an intermediate layer between the first and second electrodes; a passivation layer on the insulating layer; and a metal layer on the passivation layer at an outer region adjacent to the active area, separated from the first electrode, and contacting the second electrode and the signal wiring, wherein a first opening is in the passivation layer at the outer region, and the metal layer contacts the insulating layer at the first opening.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: May 26, 2020
    Assignee: Samsung Display Co., Ltd.
    Inventors: Won-Kyu Kwak, Han-Sung Bae, Sun-Youl Lee
  • Patent number: 10665584
    Abstract: A well-less Transient Voltage Suppressor (TVS) Silicon-Controlled Rectifier (SCR) has a P+ anode region that is not in an N-well. The P+ anode region 20 is surrounded by N+ isolation regions near the surface, and a deep N+ region underneath that is formed in a p-substrate. A N+ cathode region is formed in the p-substrate. The deep N+ region has a doping of 5×1018 to 5×1019/cm3, compared to a doping of 1×1016/cm3 for a typical N-well, or a doping of 1×1013 to 1×1015/cm3 for the p-substrate. The high doping in the deep N+ region causes a recombination current that can shunt half of the anode current. Since the deep N+ region is much shallower than an N-well, the sidewall capacitance is greatly reduced, allowing for higher speed applications.
    Type: Grant
    Filed: March 7, 2019
    Date of Patent: May 26, 2020
    Assignee: Hong Kong Applied Science and Technology Research Insstitute Company, Limited
    Inventors: Chenyue Ma, Chun-Kit Yam, Xiao Huo
  • Patent number: 10658179
    Abstract: Aspects of the disclosure provide a method. The method includes providing a substrate having a structure formed on the substrate, and forming a spacer layer on the structure. Then, the method includes forming a mask layer over the spacer layer. The mask layer includes a first layer, a second layer over the first layer, and a third layer over the second layer. Further, the method includes patterning the third layer of the mask layer, and etching the first layer and the second layer of the mask layer with a dry etching process using the third layer as an etch mask to form an opening that exposes a portion of the spacer layer. Then, the method includes removing the second layer using a wet etchant before a formation of a backfill material layer in the opening and over the first layer.
    Type: Grant
    Filed: August 17, 2018
    Date of Patent: May 19, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Nai-Chia Chen, Wan Hsuan Hsu, Chia-Wei Wu, Neng-Jye Yang, Chun-Li Chou
  • Patent number: 10651337
    Abstract: The present disclosure relates to a method for manufacturing a semiconductor light emitting device, a semiconductor device including the supporting substrate, and a method for manufacturing the supporting substrate, in which the method includes: providing a first substrate having a first face and a second face opposite to the first face; forming a groove in the first substrate in a direction from the first face to the second face; forming a conducting part in the groove; bonding a second substrate to the first face of the first substrate; and forming, on the second face, a first conducting pad to be in electrical communication with the conducting part.
    Type: Grant
    Filed: October 22, 2015
    Date of Patent: May 12, 2020
    Inventor: Sang Jeong An
  • Patent number: 10651075
    Abstract: A method for semiconductor fabrication includes mounting a wafer onto a first wafer table. The first wafer table includes a first set of pins that support the wafer, the first set of pins having a first pitch between adjacent pins. The method further includes forming a first set of overlay marks on the wafer; and transferring the wafer onto a second wafer table. The second wafer table includes a second set of pins having a second pitch between adjacent pins. The second set of pins are individually and vertically movable, and the second pitch is smaller than the first pitch. The method further includes moving a portion of the second set of pins such that a remaining portion of the second set of pins supports the wafer and the remaining portion has the first pitch between adjacent pins.
    Type: Grant
    Filed: November 27, 2018
    Date of Patent: May 12, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chi-Hung Liao, Min-Cheng Wu
  • Patent number: 10635125
    Abstract: A two-wire load control device may be configured to compute an accurate estimate of real-time power consumption by a load that is electrically connected to, and controlled by, the two-wire load control device. The load control device may be adapted to measure a voltage drop across the device during a first portion of a half-cycle of an AC waveform provided to the device. The device may be further configured to estimate a voltage drop across the load during the second portion of the half-cycle. The estimated voltage drop may be based on the measured voltage drop. The device may be further configured to measure a current supplied to the load during a second portion of the half-cycle. The device may be configured to estimate power consumed by the load based on the measured current and the estimated voltage drop.
    Type: Grant
    Filed: September 7, 2018
    Date of Patent: April 28, 2020
    Assignee: Lutron Technology Company LLC
    Inventors: Matthew Robert Blakeley, William Zotter
  • Patent number: 10634943
    Abstract: The present disclosure provides a display substrate and a manufacturing method thereof, and a display panel. The display substrate has a display area and a peripheral area surrounding the display area, wherein a plurality of force sensors is provided in the peripheral area and the plurality of force sensors is made of polysilicon material, in a direction perpendicular to the display substrate, a first layer is provided directly under a layer where the plurality of force sensors is located, and a second layer is provided directly above the layer where the plurality of force sensors is located, a Young's modulus of at least one of the first layer and the second layer is larger than a Young's modulus of silicon oxide. The technical solution of the present disclosure can improve the detection accuracy of the force sensor with respect to a force.
    Type: Grant
    Filed: March 13, 2018
    Date of Patent: April 28, 2020
    Assignee: SHANGHAI TIANMA MICRO-ELECTRONICS CO., LTD.
    Inventors: Feng Lu, Koji Shigamura
  • Patent number: 10605797
    Abstract: The present disclosure relates to methods and apparatus for determining a gas-oil ratio based on downhole fluid analysis measurements and calibrated gas-oil ratio parameters. According to certain embodiments, the parameters for calculating the gas-oil ratio may be calibrated using historical data from the reservoir. For example, previously determined gas-oil ratios may be employed to calibrate the parameters to the reservoir. The calibrated parameters may then be employed during sampling operations to determine the gas-oil ratio.
    Type: Grant
    Filed: February 12, 2015
    Date of Patent: March 31, 2020
    Assignee: SCHLUMBERGER TECHNOLOGY CORPORATION
    Inventors: Youxiang Zuo, Vinay K. Mishra, Oliver C. Mullins
  • Patent number: 10605680
    Abstract: In various aspects, embodiments of the disclosure are generally directed to measuring static and dynamic forces of a body using sensors. In particular, a sensor may include a first layer serving as a flexible support material; a second layer on the first layer, the second layer serving as a sensing material; and a third layer on the second layer, the third layer comprising an insulating material. Further, the second layer and the third layer may be coupled using a first electrode comprising a first conductive thread and a first non-conductive thread, and the first conductive thread may be embedded in the second layer. Also, the first layer and the second layer may be further coupled using a second electrode comprising a second conductive thread and a second non-conductive thread, and the second conductive thread may be embedded in the second layer.
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: March 31, 2020
    Assignee: Nextiles Inc.
    Inventor: George L. Sun
  • Patent number: 10603049
    Abstract: A drill tool for implant surgery including a first drill part having a first, smaller diameter for drilling a recess for an implant post and a second drill part having a second, larger diameter for drilling a recess for an implant hat is disclosed. The second drill part has one or more shape cutting edges and one or more sharp pre-cutting edges extending beyond said one or more shape cutting edges.
    Type: Grant
    Filed: February 8, 2016
    Date of Patent: March 31, 2020
    Assignee: EPISURF IP-MANAGEMENT AB
    Inventors: Nina Bake, Karin Wermelin, Manuel Otero Quevedo, Niklas Hero
  • Patent number: 10607996
    Abstract: A construction of integrated circuitry comprises a horizontal longitudinally-elongated conductive line. A horizontal longitudinally-elongated void space extends longitudinally along opposing longitudinal sides of the conductive line. The void space along each of the opposing longitudinal sides has cyclically varying height longitudinally along the conductive line. Methods independent of the above structure are disclosed.
    Type: Grant
    Filed: December 26, 2018
    Date of Patent: March 31, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Takashi Sasaki