Abstract: A semiconductor component, in particular for a varactor, having at least one first semiconductor layer and a second semiconductor layer. At least two identical surface electrodes are arranged directly or indirectly on the second semiconductor layer facing away from the first semiconductor layer in order to form two anti-serially connected diodes. The surface electrodes are arranged in an interacting manner such that a load carrier zone which forms the common counter electrode for the surface electrodes is arranged in the first semiconductor layer at least in the operating state, and at least one control contact for controlling the potential of the load carrier zone is provided in a region of the load carrier zone on the second semiconductor layer face facing away from the first semiconductor layer.

Abstract: A device includes a semiconductor substrate. A step is formed at a periphery of the semiconductor substrate. A first layer, made of polysilicon doped in oxygen, is deposited on top of and in contact with a first surface of the substrate. This first layer extends at least on a wall and bottom of the step. A second layer, made of glass, is deposited on top of the first layer and the edges of the first layer. The second layer forms a boss between the step and a central area of the device.

Abstract: A semiconductor device according to the present embedment includes a substrate having a first region provided with a semiconductor element and a second region provided from the first region to an end. A material film is provided above the first and second regions. A first metal film is provided on the material film in the second region or on the material film between the first region and the second region. A trench, which caves in toward the substrate from a surface of the material film in the first region and from a surface of the material film under the first metal film, is provided in the material film between the first metal film and the first region.

Abstract: An npnp layered switch is modified to have a composite anode structure. Instead of the continuous p-type bottom anode layer of a typical npnp IGTO device, thyristor, or IGBT, the composite anode is formed of a segmented p-type layer with gaps containing n-type semiconductor material. The n-type material forms a majority carrier path between the bottom anode electrode and the n-type collector of the vertical npn bipolar transistor. When a trenched gate is biased high, the majority carrier path is created between the bottom anode electrode and the top cathode electrode. Such a current path operates at very low operating voltages, starting at slightly above 0 volts. Above operating voltages of about 1.0 volts, the npnp layered switch operates normally and uses regenerative bipolar transistor action to conduct a vast majority of the current. The two current paths conduct in parallel.

Abstract: Structures for a bidirectional switch and methods of forming such structures. A substrate contact is formed in a trench defined in a substrate. A substrate includes a trench and a substrate contact in the trench. A bidirectional switch, which is on the substrate, includes a first source/drain electrode, a second source/drain electrode, an extension region between the first source/drain electrode and the second source/drain electrode, and a gate structure. A substrate-bias switch, which is on the substrate, includes a gate structure, a first source/drain electrode coupled to the substrate contact, a second source/drain electrode coupled to the first source/drain electrode of the bidirectional switch, and an extension region laterally between the gate structure and the first source/drain electrode.

Abstract: Embodiments disclosed herein include semiconductor devices and methods of forming such semiconductor devices. In an embodiment, a method of fabricating a semiconductor device comprises, forming a first grating of parallel first lines, forming a second grating of parallel second lines, wherein the second lines are substantially orthogonal to the first lines, and wherein the first lines and second lines define a plurality of first openings, disposing a conformal mask layer over the first lines and the second lines, wherein the conformal mask layer partially fills the first openings and defines a second opening within each of the first openings, disposing a hardmask over the conformal mask layer, wherein the hardmask fills the second openings, patterning third openings into the hardmask, wherein the third openings clear the hardmask from at least one of the second openings, and removing the mask layer proximate to cleared second openings to clear first openings.

Abstract: In a computer-implemented method of assessing driving performance using route scoring, driving data indicative of operation of a vehicle while the vehicle was driven on a driving route may be received. Road infrastructure data indicative of one or more features of the driving route may also be received. A route score for the driving route may be calculated using the road infrastructure data, and a driving performance score for a driver of the vehicle may be calculated using the driving data and the route score for the driving route. Data may be sent to a client device via a network to cause the client device to display the driving performance score and/or a ranking based on the driving performance score, and/or the driving performance score may be used to determine a risk rating for the driver of the vehicle.

Abstract: A light emitting chip including a first LED sub-unit, a second LED sub-unit disposed on the first LED sub-unit, a third LED sub-unit disposed on the second LED sub-unit, a passivation layer disposed on the third LED sub-unit, and a first connection electrode electrically connected to at least one of the first, second, and third LED sub-units, in which the first connection electrode and the third LED sub-unit form a first angle defined between an upper surface of the third LED sub-unit and an inner surface of the first connection electrode that is less than about 80°.

Abstract: Provided are a display device, a mask assembly, and an apparatus and a method for manufacturing the display device. The mask assembly includes: a mask frame; at least two mask sheets installed on the mask frame, each of the mask sheets including a plurality of openings; and at least two thin shielding plates installed on the mask frame such that the thin shielding plates are spaced apart from each other and shield a portion of the plurality of openings of each mask sheet, wherein one of the mask sheets and the thin shielding plates includes a shielding portion between the thin shielding plates spaced apart from each other, the shielding portion selectively blocking at least portions of the openings so as to form a deposition region having a shape other than a rectangle or a square.

Abstract: A method of depositing a material on one of two, but not both, sidewalls of a raised structure formed on a substrate includes tilting a normal of the substrate away from a source of the deposition material or tilting the source of the deposition material away from the normal of the substrate. The method may be implemented by a plasma-enhanced chemical vapor deposition (PECVD) technique.

Abstract: An image sensor includes an array of readout circuits in non-organic technology and photodiodes made of organic materials.

Abstract: Superconducting tunnel junctions for use in, for instance, quantum processors. In one example, a quantum processor can have at least one qubit structure. The at least one qubit structure includes a first aluminum layer, a second aluminum layer, and a crystalline dielectric layer disposed between the first aluminum layer and the second aluminum layer. The crystalline dielectric layer includes a spinel crystal structure.

Abstract: A semiconductor device includes an epitaxial substrate. The epitaxial substrate includes a substrate. A strain relaxed layer covers and contacts the substrate. A III-V compound stacked layer covers and contacts the strain relaxed layer. The III-V compound stacked layer is a multilayer epitaxial structure formed by aluminum nitride, aluminum gallium nitride or a combination of aluminum nitride and aluminum gallium nitride.

Abstract: A Taiko wafer ring cut process method is provided. The Taiko wafer ring cut process method includes the following steps. A Taiko wafer is disposed on the platform. The Taiko wafer is performing by laser ring cutting so that a Taiko ring and an edge portion of the Taiko wafer are separated from a wafer portion of the Taiko wafer. The wafer portion of the Taiko wafer is adhered to a frame.

Abstract: Embodiments are directed to high electron mobility transistor (HEMT) devices and methods. One such HEMT device includes a substrate having a first surface, and first and second heterostructures on the substrate and facing each other. Each of the first and second heterostructures includes a first semiconductor layer on the first surface of the substrate, a second semiconductor layer on the first surface of the substrate, and a two-dimensional electrode gas (2DEG) layer between the first and second semiconductor layers. A doped semiconductor layer is disposed between the first and second heterostructures, and a source contact is disposed on the first heterostructure and the second heterostructure.

Abstract: A non-blended dataset related to a same surveyed area as a blended dataset is used to deblend the blended dataset. The non-blended dataset may be used to calculate a model dataset emulating the blended dataset, or may be transformed in a model domain and used to derive sparseness weights, model domain masking, scaling or shaping functions used to deblend the blended dataset.

Abstract: Package structures and methods for forming the same are provided. The package structure includes an integrated circuit die and a package layer surrounding the integrated circuit die. The package structure also includes a redistribution structure over the package layer and electrically connected to the integrated circuit die. The redistribution structure includes a passivation layer and a conductive layer formed in the passivation layer. The integrated circuit die further includes a connector formed over the conductive layer and covered a top surface of the passivation layer. In addition, a bottom surface of the connector and a top surface of the connector are both wider than a neck portion of the connector.

Abstract: The present disclosure relates to a novel neuron circuit using a p-n-p-n diode to realize small size and low power consumption. The neuron circuit according to one embodiment of the present disclosure may generate potential by charging current input from synapses through a capacitor. In this case, when the generated potential exceeds a critical value, the neuron circuit may generate and output a spike voltage corresponding to the generated potential using a p-n-p-n diode connected to the capacitor.

Abstract: An integrated enhancement/depletion mode high electron mobility transistor (HEMT) includes a substrate, a buffer layer, a first barrier layer, a second barrier layer, a first source, a first drain a first gate, a second source, a second drain, and a second gate. The buffer layer is on the substrate. The first barrier layer is on the buffer layer, and the second barrier layer is on the first barrier layer. The second barrier layer covers a portion of the first barrier layer. The first source, the first drain, and the first gate are on the first barrier layer, and the second source, the second drain, and the second gate are on the second banner layer.

Abstract: A method for fabricating stacked resistive memory with individual switch control is provided. The method includes forming a first random access memory (ReRAM) device. The method further includes forming a second ReRAM device in a stacked nanosheet configuration on the first ReRAM device. The method also includes forming separate gate contacts for the first ReRAM device and the second ReRAM device.