Abstract: A micromechanical component for a sensor device, including a seismic mass, which is situated at and/or in a mounting and which includes a first electrode area, a second electrode area electrically insulated from the first electrode area, and a connecting area made up of at least one electrically insulating material. The first electrode area and the second electrode area each mechanically contact the connecting area and are connected to one another via the connecting area. At least one first conductive area of the first electrode area and a second conductive area of the second electrode area are structured out of a first semiconductor and/or metal layer. The first electrode area also includes a third conductive area. The second electrode area also includes a fourth conductive area. The third conductive area and the fourth conductive area are structured out of a second semiconductor and/or metal layer.

Abstract: Embodiments disclosed herein include electronic systems with vias that include a horizontal and vertical portion in order to provide interconnects to stacked components, and methods of forming such systems. In an embodiment, an electronic system comprises a board, a package substrate electrically coupled to the board, and a die electrically coupled to the package substrate. In an embodiment the die comprises a stack of components, and a via adjacent to the stack of components, wherein the via comprises a vertical portion and a horizontal portion.

Abstract: A carrier substrate includes a base layer, an antireflection layer, and an energy absorption layer, wherein the antireflection layer is formed on one surface of the base layer and allows an elastic wave generated by a first laser beam transmitted through an element adhesively bonded to the antireflection layer to be transmitted through the base layer without being reflected towards the element, the first laser beam being applied to the element through a source substrate of the element, and the energy absorption layer is formed between the base layer and the antireflection layer to be aligned with the element, and evaporates upon energy absorption.

Abstract: A three-dimensional (3D) memory structure includes a memory array formed on a side of a substrate, a far-back-end-of-line (FBEOL) structure formed on the memory array, and a back-end-of-line (BEOL) structure formed on another side of the substrate opposite the side on which the memory array and the BEOL structure are formed. Methodologies to fabricate the 3D memory structure are also disclosed and include forming the memory array on the substrate, forming the FBEOL on the memory array, flipping the substrate, and forming the BEOL on the opposite side of the substrate. Alternative 3D memory structures and fabrication methodologies are also disclosed.

Abstract: A semiconductor memory device, and a method of manufacturing the semiconductor memory device, includes a first source layer, a second source layer on the first source layer, a stack on the second source layer, a channel structure passing through the stack and the second source layer, and a common source line passing through the stack and the second source layer. The second source layer includes an air gap and a conductive layer surrounding the air gap.

Abstract: According to one embodiment, a semiconductor device includes: a semiconductor layer including a first plane extending along a plane including a first axis and a second axis; a first electrode extending along the first axis; a second electrode extending along the second axis; and a third electrode above the first plane. The third electrode is electrically coupled to the first electrode and the second electrode, and includes a first portion, a second portion and a third portion. The first portion crosses the first electrode. The second portion crosses the second electrode. The third portion crosses the second electrode and is separate at a first end from the second portion.

Abstract: A Static Radom Access Memory (SRAM) cell includes a pass-gate transistor and a pull-down transistor. The pass-gate transistor includes a first active region and a first gate structure engaging the first active region. The pull-down transistor includes a second active region and a second gate structure engaging the second active region. The SRAM cell further includes a first isolation feature abutting the first gate structure and a second isolation feature abutting the second gate structure. The first isolation feature is spaced from the first active region of the pass-gate transistor for a first distance. The second isolation feature is spaced from the second active region of the pull-down transistor for a second distance that is larger than the first distance.

Abstract: An electronic device comprising a lower deck and an upper deck adjacent to a source. Each of the lower deck and the upper deck comprise tiers of alternating conductive materials and dielectric materials. Each of the lower deck and the upper deck also comprise an array region and one or more non-array regions. Memory pillars are in the lower deck and the upper deck of the array region and the memory pillars are configured to be operably coupled to the source. Dummy pillars are in the upper deck of the one or more non-array regions and the dummy pillars are configured to be electrically isolated from the source. Another conductive material is in the upper deck and the lower deck of the one or more non-array regions. Additional electronic devices and related systems and methods of forming an electronic device are also disclosed.

Abstract: Embodiments disclosed herein include semiconductor devices and methods of forming such semiconductor devices. In an embodiment, a method of fabricating a semiconductor device comprises, forming a first grating of parallel first lines, forming a second grating of parallel second lines, wherein the second lines are substantially orthogonal to the first lines, and wherein the first lines and second lines define a plurality of first openings, disposing a conformal mask layer over the first lines and the second lines, wherein the conformal mask layer partially fills the first openings and defines a second opening within each of the first openings, disposing a hardmask over the conformal mask layer, wherein the hardmask fills the second openings, patterning third openings into the hardmask, wherein the third openings clear the hardmask from at least one of the second openings, and removing the mask layer proximate to cleared second openings to clear first openings.

Abstract: Semiconductor devices and methods of manufacturing the same are provided. The semiconductor devices may have a memory array having two transistor (2T) memory cells, each including a non-volatile memory (NVM) transistor and a high voltage (HV) field-effect transistor (FET) as a select transistor disposed within at least one recess(es). The devices further include a logic area in which HV FETs, input/output (I/) FETs, and low voltage (LV)/core FETs are formed thereon. Other embodiments are also described.

Abstract: According to one embodiment, a display device includes a first substrate on which a light emitting element is mounted and a second substrate that faces the first substrate. The second substrate includes a reflector plate at a position above the light emitting element and facing a light emission surface of the light emitting element.

Abstract: A light emitting module including a substrate, a first light emitter and a second light emitter disposed on the substrate and spaced apart from each other, an isolation layer disposed between the first and second light emitters, and a light diffusion layer and a wavelength converter disposed on the first and second light emitters, in which the first and second light emitters include first and second light emitting regions spaced apart from each other, respectively, the wavelength converter includes a first wavelength conversion layer covering the second light emitting region, and a second wavelength conversion layer covering the first light emitting region, the light diffusion layer covers an upper surface of the first and second wavelength conversion layers, and a region between the first and second wavelength conversion layers has an area vertically overlapped with the isolation layer.

Abstract: A method for manufacturing a nitride semiconductor device including: forming an N-type region in a nitride semiconductor layer; implanting ions of an acceptor element into a region under the N-type region in the nitride semiconductor layer; and forming a first P-type region under the N-type region by subjecting the nitride semiconductor layer to heat treatment and activating the acceptor element. The forming the N-type region includes implanting ions of a donor element into the nitride semiconductor layer such that concentration of the donor element in the N-type region is equal to or greater than concentration of the acceptor element in the first P-type region. The implanting ions of the acceptor element into a region under the N-type region includes implanting ions of the acceptor element such that concentration of the acceptor element in the first P-type region is 1×1019 cm?3 or more and 1×1021 cm?3 or less.

Abstract: A memory device includes a first conductor and a charge storage film extending along a first direction; a first semiconductor of a first conductive type; a second and third semiconductor each of a second conductive type; and a stack comprising a second conductor, a first insulator, and a third conductor sequentially stacked along the first direction and each extending along a second direction. The first conductor, the charge storage film, the first semiconductor, and the stack are arranged in this order along a third direction. The second semiconductor is in contact with the first semiconductor and the second conductor, between the second conductor or the first insulator and the charge storage film.

Abstract: A device includes a semiconductor substrate. A step is formed at a periphery of the semiconductor substrate. A first layer, made of polysilicon doped in oxygen, is deposited on top of and in contact with a first surface of the substrate. This first layer extends at least on a wall and bottom of the step. A second layer, made of glass, is deposited on top of the first layer and the edges of the first layer. The second layer forms a boss between the step and a central area of the device.

Abstract: Implementations of methods of forming a plurality of semiconductor die may include forming a damage layer beneath a surface of a die street in a semiconductor substrate, singulating the semiconductor substrate along the die street into a plurality of semiconductor die, and removing one or more particulates in the die street after singulating through applying sonic energy to the plurality of semiconductor die.

Abstract: A HEMT comprising a channel layer of a first III-Nitride semiconductor material, grown on a N-polar surface of a back barrier layer of a second III-Nitride semiconductor material; the second III-Nitride semiconductor material having a larger band gap than the first III-Nitride semiconductor material, such that a positively charged polarization interface and two-dimensional electron gas is obtained in the channel layer; a passivation, capping layer, of said first III-Nitride semiconductor material, formed on top of and in contact with a first portion of a N-polar surface of said channel layer; a gate trench traversing the passivation, capping layer, and ending at said N-polar surface of said channel layer; and a gate conductor filling said gate trench.

Abstract: In some embodiments, a semiconductor structure includes: a first epitaxial oxide semiconductor layer; a metal layer; and a contact layer adjacent to the metal layer, and between the first epitaxial oxide semiconductor layer and the metal layer. The contact layer can include an epitaxial oxide semiconductor material. The contact layer can also include a region comprising a gradient in a composition of the epitaxial oxide semiconductor material adjacent to the metal layer, or a gradient in a strain of the epitaxial oxide semiconductor material over a region adjacent to the metal layer.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a gate stack over the substrate. The semiconductor device structure includes a cap layer over the gate stack. The semiconductor device structure includes a protective layer over the cap layer, wherein a lower portion of the protective layer extends into the cap layer. The semiconductor device structure includes a contact structure passing through the protective layer and the cap layer.

Abstract: Provided are a black phosphorus-two dimensional material complex and a method of manufacturing the black phosphorus-two dimensional material complex. The black phosphorus-two dimensional material complex includes: first and second two-dimensional material layers, which each have a two-dimensional crystal structure and are coupled to each other by van der Waals force; and a black phosphorus sheet which between the first and second two-dimensional material layers and having a two-dimensional crystal structure in which a plurality of phosphorus atoms are covalently bonded.