Abstract: A semiconductor device including a substrate with a first region and a second region and first and second transistors in the first and second regions, respectively. The first transistor includes a first gate insulating layer on the substrate, a first etch-stop layer, and a first work function layer on the first etch-stop layer. The second transistor includes a second gate insulating layer on the substrate, a second etch-stop layer, and a second work function layer on the second etch-stop layer. At least one of the first and second work function layers is chamfered.

Abstract: A semiconductor device according to an embodiment includes a first substrate including a first insulating layer, a first conductive layer provided in the first insulating layer, a first metal layer provided in the first insulating layer, and a second metal layer provided between the first metal layer and the first conductive layer, a linear expansion coefficient of the second metal layer being higher than that of the first metal layer; and a second substrate including a second insulating layer, and a third metal layer provided in the second insulating layer, in contact with the first metal layer. The second substrate contacts with the first substrate.

Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a gate dielectric, a gate electrode, a field plate dielectric layer, and a field plate. The gate dielectric layer is arranged over a substrate and between a source region and a drain region. The gate electrode is arranged over the gate dielectric layer. The field plate dielectric layer is arranged over the substrate and between the gate dielectric layer and the drain region. The field plate is arranged over the field plate dielectric layer and is spaced apart from the gate dielectric layer.

Abstract: Electronic chip comprising: an electronic circuit; a resistive element arranged on a rear face of a substrate; two conductive vias passing through the substrate, each connected to the electronic circuit and to one of the ends of the resistive element, and masked by the resistive element; and comprising a weakening structure formed of blind holes such that each of the blind holes comprises a section, at the rear face, of shape and of external dimensions similar to those of the conductive vias, and comprises a portion of the substrate masked by the resistive element, or in which the resistive element comprises first and second parts spaced apart from each other, arranged one above the other, electrically connected to each other and together forming a coil pattern and/or several alternating, intermingled, wound up or intertwined patterns.

Abstract: A bidirectional electrostatic discharge protection device and a method for fabricating the same is disclosed. The protection device includes a heavily-doped semiconductor substrate, a first semiconductor epitaxial layer, a second semiconductor epitaxial layer, a heavily-doped area, and a lightly-doped area. The substrate, the heavily-doped area, and the lightly-doped area have a first conductivity type and the epitaxial layers have a second conductivity type. The first semiconductor epitaxial layer and the second semiconductor epitaxial layer are sequentially formed on the substrate, and the heavily-doped area and the lightly-doped area are formed in the second semiconductor epitaxial layer.

Abstract: A semiconductor integrated circuit device using nanowire FETs has a circuit block in which a plurality of cell rows each including a plurality of standard cells lined up in the X direction are placed side by side in the Y direction. The plurality of standard cells each include a plurality of nanowires that extend in the X direction and are placed at a predetermined pitch in the Y direction. The plurality of standard cells have a cell height, that is a size in the Y direction, M times (M is an odd number) as large as half the pitch of the nanowires.

Abstract: A silicon carbide device includes a silicon carbide substrate having a body region and a source region of a transistor cell. Further, the silicon carbide device includes a titanium carbide gate electrode of the transistor cell.

Abstract: A semiconductor device includes a semiconductor substrate having a cell region and a dummy region surrounding the cell region, a plurality of memory pillar structures, and a supporting layer. The memory pillar structures are on the cell region. The supporting layer is over the semiconductor substrate, interconnecting the memory pillar structures, and having a plurality of first and second opening patterns on the cell region. A first number of the memory pillar structures surround each of the first opening patterns, and a second number of the memory pillar structures surround each of the second opening patterns. The first opening patterns are different from the second opening patterns, the first number is different from the second number, and at least one of the first opening patterns and at least one of the second opening patterns are on a central portion of the cell region.

Abstract: A semiconductor device includes a semiconductor part, a terminal insulating film, a first protective film, a second electrode, a terminal electrode, a first insulating film, and a second protective film. The terminal insulating film is provided on the semiconductor part in the terminal region. The first protective film is provided on the terminal insulating film. The first and second protective films includes silicon and nitrogen. The second electrode is provided on the semiconductor part in the cell region and includes an end portion located on the first protective film. The terminal electrode is provided on the first protective film in the terminal region and is connected to the semiconductor part. The first insulating film is provided on the first protective film. The first insulating film includes hydrogen and contacts the second electrode and the terminal electrode. The second protective film covers the first insulating film.

Abstract: Embodiments herein describe techniques, systems, and method for a semiconductor device. Embodiments herein may present a semiconductor device including a substrate, and a channel area above the substrate and including a first III-V material. A source area may be above the substrate and including a second III-V material. An interface between the channel area and the source area may include the first III-V material. The source area may include a barrier layer of a third III-V material above the substrate. A current is to flow between the source area and the channel area through the barrier layer. Other embodiments may be described and/or claimed.

Abstract: A device includes a first transistor, a second transistor, and a contact. The first transistor includes a first source/drain, a second source/drain, and a first gate between the first and second source/drains. The second transistor includes a third source/drain, a fourth source/drain, and a second gate between the third and fourth source/drains. The contact covers the first source/drain of the first transistor and the third source/drain of the second transistor. The contact is electrically connected to the first source/drain of the first transistor and electrically isolated from the third source/drain of the second transistor.

Abstract: A TTV of the silicon carbide substrate is less than or equal to 3 ?m. The first main surface includes a first central region surrounded by a square having each side of 90 mm. An intersection of diagonal lines of the first central region coincides with a center of the first main surface. The first central region is constituted of nine square regions each having each side of 30 mm. A maximum LTV among the nine square regions is less than or equal to 1 ?m. An arithmetic mean roughness Sa in a second central region is less than or equal to 0.1 nm, the second central region being surrounded by a square centering on the intersection and having each side of 250 ?m.

Abstract: A protective film agent for laser dicing that includes a solution in which at least a water-soluble resin, an organic solvent, and an ultraviolet absorber are mixed and in which the content of sodium (Na) of the solution is equal to or lower than 100 ppb in weight ratio. Preferably, the solution further includes an antioxidant.

Abstract: A method of manufacturing a light emitting device includes: providing a light emitting element including a light extraction surface, an electrode-formed surface on a side opposite to the light extraction surface, lateral surfaces positioned between the light extraction surface and the electrode-formed surface, and a pair of electrodes on the electrode-formed surface; providing a covering member including a lens portion and a first recess on a side different from the lens portion; disposing the light emitting element on a bottom surface of the first recess, with the light extraction surface and the bottom surface of the first recess facing each other; and forming a reflective member in the first recess to cover the lateral surfaces of the light emitting element while at least a part of the pair of electrodes is exposed from the reflective member.

Abstract: A semiconductor structure is provided in the present invention, including a substrate having a device region and an alignment mark region defined thereon, a dielectric layer disposed on the substrate, a conductive via formed in the dielectric layer on the device region, a first trench formed in the dielectric layer on the alignment mark, a plurality of second trenches formed in the dielectric layer directly under the first trench and exposed from a bottom surface of the first trench, and a memory stacked structure disposed on the dielectric layer, directly covering a top surface of the conductive via and filling into the first trench and the second trench.

Abstract: A method is described for controlling a spin qubit quantum device that includes a semiconducting portion, a dielectric layer covered by the semiconducting portion, a front gate partially covering an upper edge of the semiconducting portion, and a back gate. The method includes, during a manipulation of a spin state, the exposure of the device to a magnetic field B of value such that g·?B·B>min(?(Vbg)). The method also includes the application, on the rear gate, of an electrical potential Vbg of value such that ?(Vbg)<g·?B·B+2|MSO|, and the application, on the front gate, of a confinement potential and an RF electrical signal triggering a change of spin state, with g corresponding to the Landé factor, ?B corresponding to a Bohr magneton, ? corresponding to an intervalley energy difference in the semiconducting portion, and MSO corresponding to the intervalley spin-orbit coupling.

Abstract: A process condition measurement wafer assembly is disclosed. In embodiments, the process condition measurement wafer assembly includes a bottom substrate and a top substrate. In another embodiment, the process condition measurement wafer assembly includes one or more electronic components disposed on one or more printed circuit elements and interposed between the top substrate and bottom substrate. In another embodiment, the process condition measurement wafer assembly includes one or more shielding layers formed between the bottom substrate and the top substrate. In embodiments, the one or more shielding layers are configured to electromagnetically shield the one or more electronic components and diffuse voltage potentials across the bottom substrate and the top substrate.

Abstract: Some embodiments include an integrated assembly having first electrodes with top surfaces, and with sidewall surfaces extending downwardly from the top surfaces. The first electrodes are solid pillars. Insulative material is along the sidewall surfaces of the first electrodes. Second electrodes extend along the sidewall surfaces of the first electrodes and are spaced from the sidewall surfaces by the insulative material. Conductive-plate-material extends across the first and second electrodes, and couples the second electrodes to one another. Leaker-devices electrically couple the first electrodes to the conductive-plate-material and are configured to discharge at least a portion of excess charge from the first electrodes to the conductive-plate-material. Some embodiments include methods of forming integrated assemblies.

Abstract: A method for manufacturing a trench isolation structure comprising forming a shallow trench having a wider upper section and a narrower lower section in a wafer surface, removing part of the silicon oxide by etching, forming a silicon oxide corner structure at a corner at a top corner of the shallow trench by thermal oxidation, depositing silicon nitride on the wafer surface to cover surfaces of the shallow trench silicon oxide and the silicon oxide corner structure, dry etching the silicon nitride on the shallow trench silicon oxide surface thereby forming masking silicon nitride residues extending into the trench, etching downwards to form a deep trench, forming silicon oxide layers on a side wall and the bottom of the deep trench, depositing polycrystalline silicon in the shallow and deep trenches, removing the silicon nitride, and forming silicon oxide in the shallow trench to cover the polycrystalline silicon.

Abstract: A method for fabricating a wafer includes providing a wafer table, wherein the wafer table includes support pins that are movable with respect to each other; identifying features of a layer to be formed on a wafer, wherein the features have a tolerance for overlay errors below a threshold; moving one or more support pins based on the features; after the moving of the one or more support pins, mounting the wafer on the wafer table; and after the mounting of the wafer on the wafer table, forming the layer on the wafer.