Abstract: Junction field effect transistors (JFETs) and related manufacturing methods are disclosed herein. A disclosed four terminal JFET includes an integrated high voltage capacitor (HVC). The JFET includes a first terminal coupled to a drain region, a second terminal coupled to the source region, a third terminal coupled to the base region, and an integrated HVC terminal coupled to an integrated HVC electrode which forms an HVC with the drain region. The JFET also includes a channel formed by a channel region. A bias on the base region fully depletes the channel of majority carriers. The channel has an unbiased concentration of majority carriers. The integrated HVC electrode is positioned relative to the channel region such that applying the bias to the integrated HVC terminal depletes the channel by at most ten percent of the unbiased concentration of majority carriers.

Abstract: A protection film for a window of a display device is capable of preventing or substantially preventing damage to a securing unit of the window. A protection film for a window of a display device includes: a protection layer; and a barrier wall on the protection layer, the protection layer having a groove at an edge of the protection layer.

Abstract: A Group III-V semiconductor structure having a semiconductor device. The semiconductor device has a source and drain recess regions extending through a barrier layer and into a channel layer. A regrown, doped Group III-V ohmic contact layer is disposed on and in direct contact with the source and drain recess regions. A gate electrode is disposed in a gap in the regrown, doped Group III-V ohmic contact layer and on the barrier layer A dielectric structure is disposed over the ohmic contact layer and over the barrier layer and extending continuously from a region over the source recess region to one side of the stem to portion and then extending continuously from an opposite side of the stem portion to a region over the drain recess region, a portion of the dielectric structure being in contact with the stem portion and the barrier layer.

Abstract: Synaptic resistors (synstors), and their method of manufacture and integration into exemplary circuits are provided. Synstors are configured to emulate the analog signal processing, learning, and memory functions of synapses. Circuits incorporating synstors are capable of performing signal processing and learning concurrently in parallel analog mode with speed, energy efficiency, and functions superior to computers.

Abstract: A composite power element includes a substrate structure, an insulation layer, a dielectric layer, a MOSFET, and a Zener diode. The MOSFET is formed in a transistor formation region of the substrate structure. The Zener diode is formed in a circuit element formation region of the substrate structure, and includes a Zener diode doping structure that is formed in the substrate structure and is covered by the insulation layer. The Zener diode doping structure includes a first P-type doped region and a first N-type doped region that is formed on an inner side of the first P-type doped region. The Zener diode further includes a Zener diode metal structure that is formed on the dielectric layer and sequentially passes through the dielectric layer and the insulation layer to be electrically connected to the first P-type doped region and the first N-type doped region.

Abstract: In an embodiment, a device includes: a first redistribution structure including a first dielectric layer; a die adhered to a first side of the first redistribution structure; an encapsulant laterally encapsulating the die, the encapsulant being bonded to the first dielectric layer with first covalent bonds; a through via extending through the encapsulant; and first conductive connectors electrically connected to a second side of the first redistribution structure, a subset of the first conductive connectors overlapping an interface of the encapsulant and the die.

Abstract: A semiconductor device includes an epitaxial substrate. The epitaxial substrate includes a substrate. A strain relaxed layer covers and contacts the substrate. A III-V compound stacked layer covers and contacts the strain relaxed layer. The III-V compound stacked layer is a multilayer epitaxial structure formed by aluminum nitride, aluminum gallium nitride or a combination of aluminum nitride and aluminum gallium nitride.

Abstract: A memory cell with hard mask insulator and its manufacturing methods are provided. In some embodiments, a memory cell stack is formed over a substrate having a bottom electrode layer, a resistance switching dielectric layer over the bottom electrode layer, and a top electrode layer over the resistance switching dielectric layer. A first insulating layer is formed over the top electrode layer. A first metal hard masking layer is formed over the first insulating layer. Then, a series of etch is performed to pattern the first metal hard masking layer, the first insulating layer, the top electrode layer and the resistance switching dielectric layer to form a first metal hard mask, a hard mask insulator, a top electrode, and a resistance switching dielectric.

Abstract: Fabricating a vertical-channel junction field-effect transistor includes forming an unintentionally doped GaN layer on a bulk GaN layer by metalorganic chemical vapor deposition, forming a Cr/SiO2 hard mask on the unintentionally doped GaN layer, patterning a fin by electron beam lithography, defining the Cr and SiO2 hard masks by reactive ion etching, improving a regrowth surface with inductively coupled plasma etching, removing hard mask residuals, regrowing a p-GaN layer, selectively etching the p-GaN layer, forming gate electrodes by electron beam evaporation, and forming source and drain electrodes by electron beam evaporation. The resulting vertical-channel junction field-effect transistor includes a doped GaN layer, an unintentionally doped GaN layer on the doped GaN layer, and a p-GaN regrowth layer on the unintentionally doped GaN layer. Portions of the p-GaN regrowth layer are separated by a vertical channel of the unintentionally doped GaN layer.

Abstract: An HEMT device, comprising: a semiconductor body including a heterojunction structure; a dielectric layer on the semiconductor body; a gate electrode; a drain electrode, facing a first side of the gate electrode; and a source electrode, facing a second side opposite to the first side of the gate electrode; an auxiliary channel layer, which extends over the heterojunction structure between the gate electrode and the drain electrode, in electrical contact with the drain electrode and at a distance from the gate electrode, and forming an additional conductive path for charge carriers that flow between the source electrode and the drain electrode.

Abstract: A display apparatus having a plurality of subpixels is provided. The display apparatus includes an array substrate and a counter substrate facing the array substrate. The counter substrate includes a base substrate; an optical compensation device on the base substrate configured to adjust light emitting brightness values of the plurality of subpixels to target brightness values respectively; and a plurality of light shielding walls on the base substrate. The optical compensation device include a plurality of photosensors configured to respectively detect light emitting brightness values of the plurality of subpixels. A respective one of the plurality of light shielding walls is configured to at least partially shield a lateral side of a respective one of the plurality of photosensors from light emitted from adjacent subpixels.

Abstract: Techniques and mechanisms for providing functionality of a transistor which comprises a conformal layer of a gate work function silicide. In an embodiment, the transistor comprises a channel region and a gate dielectric which extends and adjoins the channel region. The gate dielectric also adjoins a layer structure of the transistor, the layer structure comprising a silicide. The silicide includes silicon and a component D which comprises a non-metal element from one of Groups IIIa, IVa, or Va. In another embodiment, the silicide further comprises a component M which includes a transition metal element from one of Groups IVb, Vb, VIb, VIIB, or VIIIb and/or which includes a metal element from one of Groups IIIa, IVa, or Va.

Abstract: Electrical overstress protection for high speed applications is provided. In certain embodiments, a method of distributed and customizable electrical overstress protection for a semiconductor die is provided. The method includes configuring a heterogeneous overstress protection array that includes a customizable forward protection circuit electrically connected between a power high pad, a power low pad, and a signal pad and distributed across the semiconductor die, including selecting a number of segmented overstress protection devices from a plurality of available overstress protection devices of the customizable protection circuit.

Abstract: Electronic package structures and assembly methods are described. In an embodiment, an electronic package includes a die mounted face up on a bottom side of a package substrate, and a plurality of components on a top side of the package substrate. The plurality of components may be unmolded, and available for rework. Additional structures are included within the package substrate to provide mechanical rigidity and robustness to the package for warpage control.

Abstract: A light emitting display device includes: a substrate; a semiconductor layer disposed on the substrate; a first insulating layer disposed on the semiconductor layer; a first gate conductor disposed on the first insulating layer; a second insulating layer disposed on the first gate conductor; a second gate conductor disposed on the second insulating layer; an interlayer insulating layer disposed on the second gate conductor; a data conductor disposed on the interlayer insulating layer; a passivation layer disposed on the data conductor; a diode first electrode disposed on the passivation layer; a partition wall disposed on the diode first electrode and including an opening overlapping the diode first electrode; a light emitting layer; and a diode second electrode. The data conductor includes a first inclined surface and a second inclined surface, and an area of the first inclined surface is different from an area of the second inclined surface.

Abstract: The present disclosure relates to an imaging device, a method for manufacturing an imaging device, and an electronic device capable of reducing light entering an electric-charge holding unit in a back-illuminated imaging device. An imaging device includes: a photoelectric conversion unit; an electric-charge holding unit; a semiconductor substrate; a wiring layer; an insulation film layer; a first light-shielding film; and a second light-shielding film. The insulation film layer, the first light-shielding film, and the wiring layer are stacked on a second surface of the semiconductor substrate. The second light-shielding film includes: a first light-shielding portion extending from the first surface of the semiconductor substrate to a middle of the semiconductor substrate; a second light-shielding portion penetrating the semiconductor substrate; and a third light-shielding portion covering a part of the first surface of the semiconductor substrate.

Abstract: An epitaxial structure and a semiconductor device are provided in which the epitaxial structure includes at least a SiC substrate, a nucleation layer, and a GaN layer. The nucleation layer is formed on the SiC substrate. The material of the nucleation layer is aluminum gallium nitride doped with a dopant, the Al content in the nucleation layer changes from high to low in the thickness direction, the lattice constant of the nucleation layer is between 3.08 ? and 3.21 ?, and the doping concentration of the nucleation layer changes from high to low in the thickness direction. The GaN layer is formed on the nucleation layer.

Abstract: A semiconductor structure includes a substrate including a substrate including a first surface, a first doped region disposed under the first surface, a second doped region disposed under the first surface, and a recess indented into the substrate and disposed between the first doped region and the second doped region; a control gate structure disposed over the first doped region and electrically connected to a control bit line; a fuse gate structure disposed over the second doped region and electrically connected to a fuse bit line; and a buried word to line disposed between the control gate structure and the fuse gate structure, wherein the buried word line is disposed within the recess of the substrate.

Abstract: Provided is an IGBT power device. The device includes: a p-type collector region; an n-type drift region located above the p-type collector region; multiple first grooves, where a second groove is provided below each of the multiple first grooves; a gate structure located in the first groove and the second groove; a p-type body region located between two adjacent first grooves; an n-type emitter region located in the p-type body region; and an n-type hole charge blocking region located between two adjacent second grooves.

Abstract: According to an embodiment of the disclosure, an electronic device comprises a substrate including an active area including a light emitting area and a non-light emitting area and a non-active area around the active area, a first electrode disposed on the substrate, an organic layer disposed on the first electrode, a second electrode including a first layer disposed on the organic layer and a second layer disposed on the first layer, and an encapsulation layer disposed on the second electrode. In the active area, the first layer of the second electrode may include at least one first hole to expose a top portion of the organic layer. Thus, there may be provided an electronic device free from an increase, over time, in the number of dark spots due to foreign bodies or even with fewer dark spots.