Patents Examined by Khamdan N. Alrobaie
  • Apparatuses and methods for determining a phase relationship between an input clock signal and a multiphase clock signal
    Patent number: 10984844
    Abstract: Apparatuses and methods for determining a phase relationship between an input clock signal and a multiphase clock signal are disclosed. An example apparatus includes a clock path configured to receive a clock signal and provide internal clock signals and a command path configured to receive a command and propagate the command through the command path responsive to the internal clock signals and provide an internal command having a timing that reflects a timing of the clock signal. The example apparatus further includes a data clock path configured to receive a data clock signal and provide multiphase clock signals based on the data clock signal and provide a delayed multiphase clock signal, and further includes a clock synchronization circuit configured to receive the delayed multiphase clock signal and latch a logic level of the delayed multiphase clock signal responsive to the internal command.
    Type: Grant
    Filed: June 25, 2019
    Date of Patent: April 20, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Hyun Yoo Lee, Kang-Yong Kim
  • Hybrid sensing scheme compensating for cell resistance instability
    Patent number: 10978148
    Abstract: Various embodiments provide a hybrid sensing scheme that may compensate for cell resistance instability in semiconductor devices, such as multi-level cell (MLC) type phase-change random-access memory (PCRAM) structures. Various embodiments may achieve a stable resistance state supporting MLC applications in PCRAM cells.
    Type: Grant
    Filed: February 7, 2020
    Date of Patent: April 13, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventor: Jau-Yi Wu
  • Resistive memory apparatus and adjusting method for write-in voltage thereof
    Patent number: 10978149
    Abstract: A resistive memory apparatus and an adjusting method for write-in voltage thereof are provided. The adjusting method for write-in voltage includes: selecting an under test memory cell array in a resistive memory; performing N reset operations on a plurality of memory cells of the under test memory cell array according to a reset voltage, and performing N set operations on the memory cells of the under test memory cell array according to a set voltage, wherein n is an integer greater than 1; calculating a reset time variation rate of the reset operations and a set time variation rate of the set operations; and adjusting a voltage value of one of the set voltage and the reset voltage according to the reset time variation rate and the set time variation rate.
    Type: Grant
    Filed: May 12, 2020
    Date of Patent: April 13, 2021
    Assignee: Winbond Electronics Corp.
    Inventors: Ju-Chieh Cheng, Ying-Shan Kuo, Lih-Wei Lin, Lung-Chi Cheng
  • Semiconductor device with first-in-first-out circuit
    Patent number: 10964702
    Abstract: Apparatuses including a first-in first-out circuit are described. An example apparatus includes: a first-in first-out circuit including a first latch, a second latch and a logic circuit coupled in series. The first latch receives first data and latches the first data responsive to a first input pointer signal. The second latch receives the latched first data from the first latch and latches the received first data responsive to a second input pointer signal that has a different phase from the first input pointer signal and thus provides a second data. The logic circuit receives the second data and an output pointer signal and further provides an output data responsive to the output pointer signal.
    Type: Grant
    Filed: October 17, 2018
    Date of Patent: March 30, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Seiji Narui, Yuki Ebihara
  • Semiconductor device
    Patent number: 10957390
    Abstract: A semiconductor device 50 of the invention includes a supply voltage VCC, a plurality of registers 14, a PMOS transistor P, an AND gate 12, and a determination circuit 16. The registers 14 include a first register and a second register. The first register can keep data, and the second register can keep a check bit. The PMOS transistor P and the AND gate 12 are both connected between the supply voltage VCC and the registers 14, and both control the supply from the supply voltage VCC to the registers 14. The determination circuit 16 determines whether the check bit kept in the second register is correct or not in a DPD (deep-power-down) mode. An operating margin of the second register is worse than that of the first register. While the determination circuit 16 determines that the check bit kept in the second register is incorrect, the PMOS transistor P provides the supply voltage VCC to the registers 14.
    Type: Grant
    Filed: May 12, 2020
    Date of Patent: March 23, 2021
    Assignee: WINBOND ELECTRONICS CORP.
    Inventor: Naoaki Sudo
  • Methods and apparatus for facilitated program and erase of two-terminal memory devices
    Patent number: 10957410
    Abstract: A method for facilitating erase or program operations on two-terminal memory devices includes substantially simultaneously initiating erase cycle or program cycle for two-terminal memory devices from a first plurality of two-terminal memory devices, monitoring erase detect or program detect conditions for each of the two-terminal memory devices, and before detecting erase detect or program detect conditions for all of the two-terminal memory devices, the method includes detecting an erase detect or a program detect condition for the first two-terminal memory device from the first plurality of two-terminal memory devices, and initiating an erase cycle or a program for a second two-terminal memory device for a second plurality of two-terminal memory devices, in response to detecting the erase detect or program detect condition for the first two-terminal memory device.
    Type: Grant
    Filed: March 4, 2019
    Date of Patent: March 23, 2021
    Assignee: Crossbar, Inc.
    Inventors: Hagop Nazarian, Sang Nguyen
  • Data shaping to reduce error rates in solid state memory devices
    Patent number: 10949119
    Abstract: Systems and methods are described for reducing error rates on data storage devices by applying data shaping to data written to such devices in order to avoid error-prone states on cells within the devices. Different states of individual cells (such as those representing different bit patterns) may have different propensities for error, and these propensities may vary during operation of a device. Thus, a device as disclosed herein may determine error-prone states for a cell or group of cells, and apply data shaping to data written to such cells to reduce the likelihood that writing the data places the cell or cells into an error-prone state. Data shaping may be used, for example, to increase the occurrence of “0” bits within input data, thus avoiding error-prone low voltage states that may be used to represent a series of “1” bits.
    Type: Grant
    Filed: February 20, 2018
    Date of Patent: March 16, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: David Rozman, Stella Achtenberg, Arthur Shulkin
  • Read latency improvement method and memory system thereof
    Patent number: 10943634
    Abstract: A memory system includes a memory device, and a controller suitable for correcting errors included in request data read through a first read operation performed by the memory device in response to a read command provided from a host, and providing corrected data to the host, wherein the controller includes a first read processor suitable for performing the first read operation, a second read processor suitable for performing a second read operation, a third read processor suitable for performing a third read operation, and a fourth read processor suitable for detecting an optimal read voltage through an e-boost operation and performing a fourth read operation.
    Type: Grant
    Filed: July 19, 2019
    Date of Patent: March 9, 2021
    Assignee: SK hynix Inc.
    Inventor: Hui-Sug Jung
  • Semiconductor storage circuit, semiconductor storage apparatus, and data detection method
    Patent number: 10930340
    Abstract: A semiconductor storage circuit has: a plurality of first memory cells and a first precharge transistor connected to a first local read bit line; and a plurality of second memory cells and a second precharge transistor connected to a second local read bit line. A signal responsive to signals output to the first and second local read bit lines is output to a global read bit line via a gate circuit and an output circuit. A first transistor having a gate connected to the output of the gate circuit is provided between the first and second local read bit lines.
    Type: Grant
    Filed: October 18, 2019
    Date of Patent: February 23, 2021
    Assignee: SOCIONEXT INC.
    Inventor: Yoshinobu Yamagami
  • Memory device for updating micro-code, memory system including the memory device, and method for operating the memory device
    Patent number: 10930350
    Abstract: Provided herein may be a memory device which is capable of easily performing an update operation of a micro-code stored in the memory device. The memory device may include a first CAM block and a second CAM block, in which a micro-code is stored; and a control logic configured to control the first and second CAM blocks such that the stored micro-code is updated with a new micro-code in a micro-code update operation.
    Type: Grant
    Filed: July 24, 2019
    Date of Patent: February 23, 2021
    Assignee: SK hynix Inc.
    Inventor: Byoung Sung You
  • Integrated circuit including at least one memory cell with an antifuse device
    Patent number: 10923484
    Abstract: An integrated circuit includes a memory cell incorporating an antifuse device. The antifuse device includes a state transistor having a control gate and a second gate that is configured to be floating. A dielectric layer between the control gate and the second gate is selectively blown in order to confer a broken-down state on the antifuse device where the second gate is electrically coupled to the control gate for storing a first logic state. Otherwise, the antifuse device is in a non-broken-down state for storing a second logic state.
    Type: Grant
    Filed: August 20, 2019
    Date of Patent: February 16, 2021
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Pascal Fornara, Fabrice Marinet
  • Constructing and programming quantum hardware for robust quantum annealing processes
    Patent number: 10915832
    Abstract: Among other things, an apparatus comprises quantum units; and couplers among the quantum units. Each coupler is configured to couple a pair of quantum units according to a quantum Hamiltonian characterizing the quantum units and the couplers. The quantum Hamiltonian includes quantum annealer Hamiltonian and a quantum governor Hamiltonian. The quantum annealer Hamiltonian includes information bearing degrees of freedom. The quantum governor Hamiltonian includes non-information bearing degrees of freedom that are engineered to steer the dissipative dynamics of information bearing degrees of freedom.
    Type: Grant
    Filed: April 6, 2020
    Date of Patent: February 9, 2021
    Assignee: Google LLC
    Inventors: Masoud Mohseni, Hartmut Neven
  • Magnetic memory apparatus
    Patent number: 10916281
    Abstract: According to one embodiment, a magnetic memory apparatus includes a first stacked body and a controller. The first stacked body includes a first magnetic layer, a first counter magnetic layer, and a first intermediate layer placed between the first magnetic layer and the first counter magnetic layer. The first intermediate layer is nonmagnetic. The controller is electrically connected to the first magnetic layer and the first counter magnetic layer. The controller is configured to perform a first operation of supplying first pulse current to the first stacked body. The first pulse current includes a first constant-current period. A first electrical resistance value of the first stacked body before the supply of the first pulse current is different from a second electrical resistance value of the first stacked body after the supply of the first pulse current.
    Type: Grant
    Filed: March 12, 2019
    Date of Patent: February 9, 2021
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hideyuki Sugiyama, Kazutaka Ikegami, Naoharu Shimomura
  • Semiconductor memory device
    Patent number: 10910036
    Abstract: A semiconductor memory device, which can reduce consuming power and perform a power-off operation correctly, is provided. A flash memory of the invention includes: a low-power-voltage detection circuit detecting that a supply voltage drops to a given voltage; a high-accuracy voltage detection circuit detecting that the supply voltage drops to the given voltage; and a controller selecting the high-accuracy voltage detection circuit when an internal circuit is in an operation state, selecting the low-power-voltage detection circuit when the internal circuit is in a standby state, and performing a power-off operation in response to a detection result of the low-power-voltage detection circuit or the high-accuracy voltage detection circuit.
    Type: Grant
    Filed: May 12, 2020
    Date of Patent: February 2, 2021
    Assignee: WINBOND ELECTRONICS CORP.
    Inventor: Naoaki Sudo
  • Memory device for reducing leakage current
    Patent number: 10910030
    Abstract: A memory device including a normal memory cell array including a first magneto-resistance memory cell that is connected to a first bit line, a first source line, and a first word line, and configured to receive a selection voltage through the first word line, a monitor memory cell array including a second magneto-resistance memory cell that is connected to a first signal line and a second signal line, a gate of a cell transistor of which is configured to receive a non-selection voltage, and a body bias generator configured to sense a leakage current flowing through the first signal line and control a body voltage provided to each of a body of a cell transistor of the first magneto-resistance memory cell and a body of the cell transistor of the second magneto-resistance memory cell based on the leakage current may be provided.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: February 2, 2021
    Assignee: Samsung Electronics Co. Ltd.
    Inventors: Artur Antonyan, Hyuntaek Jung, Suk-Soo Pyo
  • Memory system
    Patent number: 10910067
    Abstract: According to one embodiment, a memory system includes a semiconductor memory and a controller. The semiconductor memory includes first to fourth word lines and first to fourth memory cells. The controller is configured to issue first and second instructions. The controller is further configured to execute a first operation to obtain a first read voltage based on a threshold distribution of the first memory cell, and a second operation to read data from the second memory cell.
    Type: Grant
    Filed: March 11, 2019
    Date of Patent: February 2, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Tsukasa Tokutomi, Masanobu Shirakawa, Marie Takada, Shohei Asami, Masamichi Fujiwara
  • Semiconductor memory device
    Patent number: 10896735
    Abstract: According to one embodiment, a semiconductor memory device includes: a memory cell array including a first memory cell, a first word line, a first circuit coupled to the first word line, a first driver used for a write operation and a read operation, a second driver used for an erase operation, and a voltage generator. The first circuit includes: a second circuit capable of electrically coupling the first word line and a first interconnect; a third circuit capable of electrically coupling the first interconnect and a second interconnect; a fourth circuit capable of electrically coupling the second interconnect and the first driver in the write and read operations; and a fifth circuit capable of electrically coupling the second interconnect and the second driver in the erase operation.
    Type: Grant
    Filed: September 9, 2019
    Date of Patent: January 19, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Bushnaq Sanad, Noriyasu Kumazaki, Yuzuru Shibazaki
  • Multiple data rate memory
    Patent number: 10878864
    Abstract: There is provided a multiple data rate memory comprising a clock splitting circuit and a multiplexing address latch. The clock splitting circuit is configured to generate first and second internal clock pulses from a rising edge of an external clock signal and to provide the first and second internal clock signals to the multiplexing address latch. The multiplexing address latch is configured to output a first address signal in response to the first internal clock pulse and a second address signal in response to the second internal clock pulse.
    Type: Grant
    Filed: February 27, 2017
    Date of Patent: December 29, 2020
    Assignee: SURECORE LIMITED
    Inventor: Stefan Cosemans
  • Semiconductor memory having both volatile and non-volatile functionality including resistance change material and method of operating
    Patent number: 10867676
    Abstract: Semiconductor memory is provided wherein a memory cell includes a capacitorless transistor having a floating body configured to store data as charge therein when power is applied to the cell. The cell further includes a nonvolatile memory comprising a resistance change element configured to store data stored in the floating body under any one of a plurality of predetermined conditions. A method of operating semiconductor memory to function as volatile memory, while having the ability to retain stored data when power is discontinued to the semiconductor memory is described.
    Type: Grant
    Filed: May 9, 2019
    Date of Patent: December 15, 2020
    Assignee: Zeno Semiconductor, Inc.
    Inventor: Yuniarto Widjaja
  • Adaptive memory cell write conditions
    Patent number: 10861544
    Abstract: A method and related apparatus for using an indication of RRAM cell resistance to determine a write condition are disclosed. A cell characteristic of an RRAM cell is determined to a finer resolution than a data read value. A write condition is selected for the RRAM cell, based on the cell characteristic. The RRAM cell is written to, using the selected write condition.
    Type: Grant
    Filed: September 21, 2017
    Date of Patent: December 8, 2020
    Assignee: Hefei Reliance Memory Limited
    Inventors: Brent Haukness, Zhichao Lu